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Your Name: _______________________________________
Final Examination Page 1 of 10 CS 150 - Sp. 97
BERKELEY • DAVIS • IRVINE • LOS ANGELES • RIVERSIDE • SAN DIEGO • SAN FRANCISCO
UNIVERSITY OF CALIFORNIA AT BERKELEY SANTA BARBARA • SANTA CRUZ Department of Electrical Engineering and Computer Sciences
CS 150 - Spring 1997 Prof. A. R. Newton
Final Examination
(Open Katz, Calculators OK, 3 hours) Include all final answers in locations indicated on these pages. Use space provided for all working. If necessary, attach additional sheets by staple at the end. State all assumptions made. BE SURE TO WRITE YOUR NAME ON EVERY SHEET.
(1) (20pts) (a) Realize the following circuit using OR gates in the first stage and AND gates in the second stage. Do not use any other gates (no inverters) and assume complements are not available.
(b) Write the output f of the circuit shown below in terms of A and B in as compact a form as possible.
1(a) (5pts) Schematic diagram:
1(b) (5pts)
f = _______________________
TOTAL /
CS 150 - Sp. 97 Page 2 of 10 Final Examination
1 (c) Reduce the following circuit to obtain the most compact ( minimum number of gates+gate inputs ) form. Use only simple gates (AND, NAND, NOR, OR, inverter, XOR, XNOR).
(d) A four-bit binary number {A,B,C,D}, where A is the most significant digit and D the least significant digit, appears on the input to a combinational logic circuit. Output X indicates whether the number is divisible by 2 without any remainder and output Y indicates if the number is divisible by 3 without remainder. Obtain the sum-of-products logic equations for X and Y with the minimum number of literals.
1(c) (5pts) Schematic:
1(d) (5pts)
X = _______________________
Y = _______________________
Additional Space for Problem 1
AB CD 00 01 11 10 00
01
11
10
AB CD 00 01 11 10 00
01
11
10
CS 150 - Sp. 97 Page 4 of 10 Final Examination
(b) Consider the following reduced state table. For the state assignment A={00}, C={01}, D={11} and E = {10}, implement the machine using JK flip-flops and logic gates only. Show your flip-flop excitation and output K-maps , the flip-flop input excitation equations , the output equation , and a schematic diagram for the final implementation using as few simple logic gates as possible.
2(b) (10 pts)
(i) Excitation and output K-maps:
(ii) Flip-flop input excitation equations and output equation:
_______________________________________ __________________________________________
_______________________________________ __________________________________________
_______________________________________ __________________________________________
(iii) Schematic diagram:
Your Name: _______________________________________
Final Examination Page 5 of 10 CS 150 - Sp. 97
(3) (20pts) A one-bit shifter is defined as follows:
−
y 1
1
x if s
x if d s
x if d s
(a) Obtain an implementation of the one-bit shifter using a single 4-input, 2 select line MUX only. (b) Show how it would be possible to build an n -bit shifter (shift each bit of an n -bit word {x 0 , x 1 , … , xn-1} one bit position up or down) using a number of your one-bit shifters from part (a) above.
3 (a) (5pts) One-bit shifter:
3(b) (5pts) n -bit shifter:
Your Name: _______________________________________
Final Examination Page 7 of 10 CS 150 - Sp. 97
(4) (20pts)
(a) Show a merger diagram for the primitive flow table shown at right. Show the merged flow table for the design.
4(a) (10pts) Merger Diagram:
Merged flow table:
Additional space for Problem 4(a)
CS 150 - Sp. 97 Page 8 of 10 Final Examination
(b) Obtain a race-free state assignment for the merged flow table shown below. You are to assign the codes for the two unassigned states and you may not use any additional states to implement the race- free assignment. Show your solution by filling in all fields (including a glitch-free output assignment for Z) on the empty table shown below.
4(b) (10pts) Final merged flow table and state assignment:
Additional space for Problem 4(b)
CS 150 - Sp. 97 Page 10 of 10 Final Examination
Additional Space for Working Problems
