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Assembler Instruction Execution: RISC vs CISC Comparison, Exercises of Digital Logic Design and Programming

Punjab Engineering College Digital Logic Design and Programming

The execution details of various assembler instructions for both risc (reduced instruction set computer) and cisc (complex instruction set computer) architectures. It includes instruction fetch, execution, and write-back cycles for specific instructions, as well as clock cycles required for each operation.

Typology: Exercises

2011/2012

Uploaded on 07/20/2012

annapurna 🇮🇳

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1

10-4.

10-10.

10-12.

a) , b)

c) d)

PC and SP are the value at the time of the instruction fetch.

PC M SP[]←SP SP 1+←R60F0F16

←

R2M255 R3+[]M255 R3+[]R2←,← MSP[]PC 2+ SP SP 1PC M M PC 200F016

++[][]←,–←,←

Register: R3, Register Indirect: 3, Immediate: 200210, Direct: 100010,

Indexed: 100310, Indexed Indirect: 100310, Relative: 300310, Relative Indirect: 300310

Sym RT MC MM/

LS MR/

PS DSA/

MS SB MA MB MD FS/

NA MO

a) SHRA0 000090D000100

1 (Set MSTS) 00009000000F

2 3 0 0 6000 0 0SHRA60

3 0000F0F000150

4 0 0 0 09 00 0 0 0 06 F

5 3 0 1 6000 0 0SHRA30

6 2 1 4 0F 00 0 0 0 00 D

b) RLC0 000090D000100

1 (Set MSTS) 00009000000F

2 3 0 0 6000 0 0RLC60

3 0000F0F0001BD

4 0 0 0 09 00 0 0 0 06 F

5 3 0 1 6000 0 0RLC20

6 2 1 4 0F 00 0 0 0 00 D

c) BV0 3 0 0 4000 0 0BRA0

1 2150000000000

R9SD

←

R9R9

←

z: CAR SHRA6

←

DD DD 15

()

DD 15:1

()←

R9R91–

←

z : CAR SHRA3

←

DD DD CAR WB0ROM

()←

,

←

R9SD

←

R9R9

←

z: CAR RLC6

←

DD DD 14 :0

()

C

←CDD15

()←,

R9R91–

←

z: CAR RLC2

←

DD DD CAR WB0ROM

()←

,

←

V: CAR BRA

←

CAR INT0(ROM)

←

MWB0 is the write back routine for the Multiply Operation.

Sym RT MC MM

/LS MR

/PS DSA

/MS SB MA MB MD FS

/NA MO

MUL0 0 0 0 09 10020 10 0

1 0 0 0 0A 0F 0 0 0 10 0

2 0000F00000100

3 0 0 0 0D 0D 0 0 0 17 D

4 3 0 1 3 00000MUL60

5 0000F0A00002D

6 0000F0F00017D

7 0 0 0 09 00 0 0 0 06 F

8 3 0 0 6 00000MWB00

9 3 0 0 0 00000MUL30

R916

←

R10 DD

←

DD R0

←

SD rorc SD

()←

C: CAR MUL6

←

DD DD R10+

←

DD rorc D D

()←

R9R91–

←

z: CAR MW B0

←

CAR MUL3

←

docsity.com

Discover Exercises of Digital Logic Design and Programming Punjab Engineering College

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a) , b)

c) d)

PC and SP are the value at the time of the instruction fetch.

PC ← M SP [ ] SP ← SP + 1 R 6 ← 0 F 0 F 16

R 2 ← M [ 255 + R 3 ] , M [ 255 + R 3 ] ← R 2 M SP [ ] ← PC + 2 , SP ← SP – 1 , PC ← M M PC [ [ + 2 + 00 F 0 16 ]]

Register: R3, Register Indirect: 3, Immediate: 2002 10 , Direct: 1000 10 ,

Indexed: 1003 10 , Indexed Indirect: 1003 10 , Relative: 3003 10 , Relative Indirect: 3003 10

Sym RT MC

MM/

LS

MR/

PS

DSA/

MS

SB MA MB MD

FS/

NA

MO

a) SHRA0 0 0 0 09 0D 0 0 0 10 0 1 (Set MSTS) 0 0 0 09 0 0 0 0 00 F 2 3 0 0 6 00 0 0 0 SHRA6 0 3 0 0 0 0F 0F 0 0 0 15 0 4 0 0 0 09 00 0 0 0 06 F 5 3 0 1 6 00 0 0 0 SHRA3 0 6 2 1 4 0F 00 0 0 0 00 D b) RLC0 0 0 0 09 0D 0 0 0 10 0 1 (Set MSTS) 0 0 0 09 0 0 0 0 00 F 2 3 0 0 6 00 0 0 0 RLC6 0 3 0 0 0 0F 0F 0 0 0 1B D 4 0 0 0 09 00 0 0 0 06 F 5 3 0 1 6 00 0 0 0 RLC2 0 6 2 1 4 0F 00 0 0 0 00 D c) BV0 3 0 0 4 00 0 0 0 BRA 0 1 2 1 5 00 00 0 0 0 00 0

R 9 ← SD R 9 ← R 9 z : CAR ←SHRA DD ← DD ( 15 ) DD ( 15:1) R 9 ← R 9 – 1 z : CAR ← SHRA 3 DD ← DD CAR , ← WB 0 ( RO M ) R 9 ← SD R 9 ← R 9 z : CAR ←RLC DD ← D D ( 14:0) C , C ← DD ( 15 ) R 9 ← R 9 – 1 z : CAR ← RLC 2 DD ← DD CAR , ← WB 0 ( RO M ) V : CAR ← BRA CAR ←INT0(ROM)

MWB0 is the write back routine for the Multiply Operation.

Sym RT MC

MM

/LS

MR

/PS

DSA

/MS

SB MA MB MD

FS

/NA

MO

MUL0 0 0 0 09 10 0 2 0 10 0

1 0 0 0 0A 0F 0 0 0 10 0

2 0 0 0 0F 00 0 0 0 10 0

3 0 0 0 0D 0D 0 0 0 17 D

4 3 0 1 3 00 0 0 0 MUL6 0

5 0 0 0 0F 0A 0 0 0 02 D

6 0 0 0 0F 0F 0 0 0 17 D

7 0 0 0 09 00 0 0 0 06 F

8 3 0 0 6 00 0 0 0 MWB0 0

9 3 0 0 0 00 0 0 0 MUL3 0

R 9 ← 16 R 10 ← D D DD ← R 0 SD ← rorc SD ( ) C : CAR ←MUL DD ← DD + R 10 DD ← rorc D D ( ) R 9 ← R 9 – 1

z : CAR ← MWB 0

CAR ←MUL

Assembler Instruction Execution: RISC vs CISC Comparison, Exercises of Digital Logic Design and Programming

Related documents

Partial preview of the text

Download Assembler Instruction Execution: RISC vs CISC Comparison and more Exercises Digital Logic Design and Programming in PDF only on Docsity!

a) , b)

c) d)

PC and SP are the value at the time of the instruction fetch.

PC ← M SP [ ] SP ← SP + 1 R 6 ← 0 F 0 F 16

R 2 ← M [ 255 + R 3 ] , M [ 255 + R 3 ] ← R 2 M SP [ ] ← PC + 2 , SP ← SP – 1 , PC ← M M PC [ [ + 2 + 00 F 0 16 ]]

Register: R3, Register Indirect: 3, Immediate: 2002 10 , Direct: 1000 10 ,

Indexed: 1003 10 , Indexed Indirect: 1003 10 , Relative: 3003 10 , Relative Indirect: 3003 10

MM/

LS

MR/

PS

DSA/

MS

SB MA MB MD

FS/

NA

MO

MWB0 is the write back routine for the Multiply Operation.

MM

/LS

MR

/PS

DSA

/MS

SB MA MB MD

FS

/NA

MO

MUL0 0 0 0 09 10 0 2 0 10 0

1 0 0 0 0A 0F 0 0 0 10 0

2 0 0 0 0F 00 0 0 0 10 0

3 0 0 0 0D 0D 0 0 0 17 D

4 3 0 1 3 00 0 0 0 MUL6 0

5 0 0 0 0F 0A 0 0 0 02 D

6 0 0 0 0F 0F 0 0 0 17 D

7 0 0 0 09 00 0 0 0 06 F

8 3 0 0 6 00 0 0 0 MWB0 0

9 3 0 0 0 00 0 0 0 MUL3 0

z : CAR ← MWB 0

docsity.com

Problem Solutions – Chapter 10

Cycle 1: PC = 10F

Cycle 2: PC -1 = 110, IR = 4418 2F01 16

Cycle 3: PC -2 = 110, RW = 1, DA = 01, MD = 0, BS = 0, PS = X, MW = 0, FS = 02, SH = 01, MA = 0, MB = 1

BUS A = 0000 001F, BUS B = 0000 2F

Cycle 4: RW = 1, DA = 01, MD = 0, D0 = 0000 2F20, D1 = XXXX XXXX, D2 = 0000 00000

Cycle 5: R1 = 0000 2F

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

MOV R7, R

SUB R8, R8, R

ADD R8, R8, R

a) MOV R7, R6 b)

SUB R8, R8, R

ADD R8, R8, R

NOP

SUB R7, R7, R

AND R8, R

NOP

BNZ R7, 000F

NOP

OR R5, R

NOP

a) LD R1, INDEX

LD R2, ADDRESS

ADD R3, R2, R

LD R4, R

SBI R4, R4, 1

ST R3, R

Time = 10 RISC Clock Cycles

b) IF = 2 CISC Clock Cycles

1OF = 4 CISC Clock Cycles

EX = 1 CISC Clock Cycles

WB = 2 CISC Clock Cycles

INT = 1 CISC Clock Cycles