Cache I-Assembly Language, Microprocessors and Computer Architecture-Lecture Slides, Slides of Computer Architecture and Organization

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Cache z^ Small amount of fast memory z^ Sits between normal main memory andCPU z^ May be located on CPU chip or module

Cache/Main Memory Structure

Cache Read Operation - Flowchart

Typical Cache Organization

Size does matter z^ Cost^ z^ More cache is expensive z^ Speed^ z^ More cache is faster (up to a point)^ z^ Checking cache for data takes time

Mapping Function z^ Cache of 64kByte z^ Cache block of 4 bytes^ z^ i.e. cache is 16k (

14 ) lines of 4 bytes

z^ 16MBytes main memory z^ 24 bit address^24 z^ (2^ =16M)

Direct Mapping Address Structure^ Tag s-r^ z^ 24 bit address^ z^ 2 bit word identifier (4 byte block)^ z^ 22 bit block identifier^ z^ 8 bit tag (=22-14)^ z^ 14 bit slot or line^ z^ No two blocks in the same line have the same Tagfield^ z^ Check contents of cache by finding line and checkingTag

Line or Slot r^

Word w 8

14

Direct Mapping Cache Line Table^ z^ Cache line^

Main Memory blocks held z^0

s0, m, 2m, 3m…2-m z^1

s1,m+1, 2m+1…2 -m+ z^ m-^

m-1, 2m-1,3m-1…

s-1 docsity.com

Direct Mapping Example

Direct Mapping Summary z^ Address length = (s + w) bits z^ Number of addressable units = 2

s+w^ words or bytes z Block size = line size = 2

w^ words or bytes z^ Number of blocks in main memory = 2

s+ w^ w^ s/2= 2^ z Number of lines in cache = m = 2

r z^ Size of tag = (s – r) bits

Associative Mapping z^ A main memory block can load into anyline of cache z^ Memory address is interpreted as tag andword z^ Tag uniquely identifies block of memory z^ Every line’s tag is examined for a match z^ Cache searching gets expensive

Tag^ 22 bit^

Word2 bit

Associative Mapping Address Structure z^ 22 bit tag stored with each 32 bit block of data z^ Compare tag field with tag entry in cache to checkfor hit z^ Least significant 2 bits of address identify which 8bit word is required from 32 bit data block

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Associative Mapping Example

Associative Mapping Summary^ z^ Address length = (s + w) bits^ z^ Number of addressable units = 2

s+w^ words or bytes z Block size = line size = 2

w^ words or bytes z^ Number of blocks in main memory = 2

s+ w^ w^ s/2= 2^ z Number of lines in cache = undetermined z Size of tag = s bits