Calculator Design
Calculator has 4 functions:
Add
Subtract
Shift left
Shift right
Calculator can handle 4 requests in parallel
All 4 requestors use separate input signals
All requestors have equal priority
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Calculator Design - Functional Verification - Lecture Slides, Slides of Computer Science
These are the Lecture Slides of Functional Verification which includes Reusable Verification Components, Verilog Implementation, Implementation, Autonomous Generation and Monitoring, Input and Output Paths, Verifying Configurable Designs, Reusable Test Harness, Testcase Specific Code, Abstraction etc. Key important points are: Calculator Design, Add, Subtract, Shift Left, Shift Right, Requestors, Separate Input Signals, Output Description, Input Commands, Input Data
Typology: Slides
2012/2013
1 / 6
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Calculator has 4 functions:
Add Subtract Shift left Shift right
Calculator can handle 4 requests in parallel
All 4 requestors use separate input signals All requestors have equal priority
Input/Output description
c_clk
out_resp2<0:1>
req1_data_in<0:31>
req1_cmd_in<0:3> out_data1<0:31>
req4_cmd_in<0:3>
req3_cmd_in<0:3>
req2_cmd_in<0:3>
req4_data_in<0:31>
req3_data_in<0:31>
req2_data_in<0:31>
reset<0:7>
out_data4<0:31>
out_data3<0:31>
out_data2<0:31>
out_resp4<0:1>
out_resp3<0:1>
out_resp1<0:1>
calc_top
Outputs
Response line definition
- 0 - no response
- 1 - successful operation completion
- 2 - invalid command or overflow/underflow erro
- 3 - Internal error Data
- Valid result data on output lines accompanies response (same cycle)
Other information
Clocking
- When using a cycle simulator, the clock should be held high (c_clk in the calculator model)
- The clock should be toggled when using an event simula Calculator priority logic
- Priority logic works on first come first serve algorithm
- Priority logic allows for 1 add or subtract at a time and one shift operation at a time