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A computer engineering exam from fall 2010. It consists of 4 problems to be solved within 5 pages. The exam is closed book and closed note, and calculators are not permitted. The problems cover various topics such as incomplete circuits, boolean algebra, karnaugh maps, and mixed logic design.
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4 problems, 5 pages Exam One 22 September 2010
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have
a question, raise your hand and I will come to you. Please work the exam in pencil and do not
separate the pages of the exam. For maximum credit, show your work.
Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 5 pages Exam One 22 September 2010
Problem 1 (3 parts, 30 points) Incomplete Circuits
The three parts below contain (A) a pull up network, (B) a pull down network, and (C) an
expression to be implemented. For (A) and (B), complete the missing complementary switching
networks so the circuit contains no floats or shorts and write the Boolean expression computed
by the completed circuit. For (C), design the entire switching network. Assume the inputs and
their complements are available.
OUTx =
OUTy =
OUTz = ๎^ A ๎^ B ๎โ D ๎ C โ ๎^ E^ ๎ F^ ๎
4 problems, 5 pages Exam One 22 September 2010
Problem 3 (2 parts, 24 points) Karnaugh Maps
Part A (12 points) For the follow expression, derive a simplified sum of products expression
using a Karnaugh Map. Circle and list all prime implicants, indicating which are essential.
Out = A โ B โ C โ D ๎ B โ C โ D ๎ A โ B โ C ๎ A โ B โ C โ D ๎ A โ B โ C
prime implicants
essential? yes no
simplified SOP expression
Part B (12 points) For the follow expression, derive a simplified product of sums expression
using a Karnaugh Map. Circle and list all prime implicants, indicating which are essential.
Out =๎ B ๎ C ๎ D ๎โ ๎ A ๎ B ๎ D ๎โ ๎ A ๎ C ๎ D ๎โ ๎ A ๎ B ๎ D ๎โ ๎ A ๎ B ๎ D ๎
prime implicants
essential? yes no
simplified POS expression
4 problems, 5 pages Exam One 22 September 2010
Problem 4 (2 parts, 26 points) Mixed Logic Design
Part A (12 points) The following design has no supporting documentation. Derive the desired
Boolean expression and the implementation cost (in CMOS transistors).
Part B (14 points) Now reimplement this expression using NAND gates and inverters. Use
proper mixed logic notation. Determine the cost of this implementation (in transistors).
