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The instructions and problems for exam two of the computer engineering course (ece 2030b) held in fall 2009. The exam consists of four problems covering various topics such as logical functions, number systems, and digital circuits. Students are required to complete the exam in pencil and show their work. Calculators are not permitted.
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4 problems, 5 pages Exam Two 4 March 2009
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 5 pages Exam Two 4 March 2009
Problem 1 (4 parts, 24 points) Building Blocks
Part A (8 points) Consider the circuit below. Complete the truth table. Then state what logical function this circuit implements.
B Out
En (^) oops!
A B Out
0 0
1 0
0 1
1 1
This wacky circuit is
Part B (6 points) Consider the following circuit below. Determine its input priority.
Part C (4 points) Derive a simplified expression for O 1.
O 1 =
Part D (6 points) Implement a 2-input NAND using a 2-to-4 decoder and a single OR gate (which may have any number of inputs). Label the inputs A and B , and output A NAND B.
IN^0
O 0
2 to 4 decoder IN 1
O^1 O 2 O 3
4 problems, 5 pages Exam Two 4 March 2009
Problem 3 (3 parts, 24 points) “Go Figure”
Part A (12 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a six bit unsigned fixed- point and six bit two’s complement fixed-point representations.
result unsigned error? signed error?
Part B (6 points) The adder below adds two four bit numbers A and B and produces a four bit result S. Add extra digital logic to support subtraction as well as addition. Label inputs X 3 , X 2 , X 1 , X 0 , Y 3 , Y 2 , Y 1 ,
Y 0 , ADD / SUB and outputs Z 3 , Z 2 , Z 1 , Z 0.
A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0
S 3 S 2 S 1 S 0
Cout Cin
Part C (6 points) Below is a partial implementation of an overflow error detector for the adder/subtractor in part B. It detects errors in addition or subtraction of signed and unsigned numbers. Complete the implementation by filling in the dashed boxes with the appropriate error detector circuitry. For full credit,
label all the inputs using signals from part B (e.g., ADD / SUB and S 3 ) and the additional input signal
Unsigned / Signed which is 1 if the numbers being added/subtracted are two’s complement numbers and
which is 0 if the numbers are unsigned.
(^1) 2-to-1 MUX 0 Sel
Error
4 problems, 5 pages Exam Two 4 March 2009
Problem 4 (3 parts, 24 points) Registers and Latches
Part A (8 points) Implement a transparent latch using only inverters and pass gates. Label the inputs In and En , and output Out.
Part B (10 points) Implement a register below using needed muxes, latches, pass gates, and inverters (all in icon form). Complete the behavior table at right. Recall that the CLK signal indicates a full Φ 1 Φ 2 cycle; so the output should be the value at the end of a cycle (with the given inputs).
In Out
Part C (6 points) Assume the following signals are applied to your register. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out is initially zero.
In WE RE Clk Out
