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The instructions and problems for the computer engineering exam three in ece 2030 a, held in spring 2010. The exam covers various topics such as memory systems, microcode, and counters. Students are required to solve problems related to memory organization, microcode design, and toggle cell and counter design. The exam is a closed-book, closed-notes exam, and calculators are not permitted.
Typology: Exams
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Instructions: a question, raise your hand and I will come to you. Please work the exam in pencil and do not This is a closed book, closed note exam. Calculators are not permitted. If you have separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total 30 25 30 15 100
Problem Part A (10 points) Consider a 1 (3 parts, 30 points) (^) 256 Mbit DRAM chip organized as 32 million addresses Memory Systems of one byte and offset concatenate to form the memory address. Using the organization approach discussed words. Assume both the DRAM cell and the DRAM chip is square. The column number in class, answer the following questions about the chip. Express all answers in decimal. number of columns column decoder required ( n to m ) type of mux required ( n to m ) number of muxes required number of address lines in column number number of address lines in column offset Part B (10 points) Consider a byte words using DRAM chips organized as one Gbyte memory system with 16 million addresses by 128 million 16 bit words. addresses of eight word address lines for memory system chips needed in one bank banks for memory system memory decoder required ( n to m ) DRAM chips required Part C (10 points) (10 points) Design a 96M address x 4 bit memory system using 32M address x 4 bit memory chips. Label all busses and indicate bit width. Assume R/W is connected and not shown here. Use a decoder if necessary. Be sure to include the address bus, data bus, and MSEL.
Problem 3 (3 parts, 30 points) Counters Part A (10 points) Design a toggle cell using transparent latches and basic gates. Use an icon for the latch. Your toggle cell should have an active high toggle enable input TE , and an active low clear input over TE. Label all signals. Also complete the behavior table for the toggle cell. CLR , clock inputs Φ 1 and Φ 2 , and an output Out. The CLR signal has precedence
TE CLR CLK Out 0 0 ↑↓ 1 0 ↑↓ 0 1 ↑↓ 1 1 ↑↓
Part B (10 points) Now combine these toggle cells to build a Your counter should have an external clear, external count enable, and four count outputs O divide by 10 (decade) counter. 3 , O 2 , O inputs to the toggle cells are already connected. 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock Your design should support multi-digit systems.
Part C (10 points) Build a three digit decimal counter (0 - 999) using three decade counters drawn below. Use any basic gates you require. Assume clock inputs are already connected.
Out Count^ Max^ Divide by 10 CE
Out Count^ Divide by 10^ Max CLR
Out Count^ Divide by 10^ Max CLR (^) CE
Problem Part A (9 points) 4 (2 parts, 15 points) Consider the following input and output values for a shift operation. Determine Microcode the shift Input Value type and amount Output Value required to achieve the listed transformation. I/Os are in hexadecimal. Shift Type Shift Amount (signed decimal value) 87654321 32187654 87654321 54321000 87654321 FFFFFF Part B (6 points) Consider the following input and output values for a logical operation. Determine the logical function and function code (in hexadecimal) required for the operation.
87654321 X Input^ 0000FFFFY Input^ 0000FFFFOutput^ Logical Function^ Function Code 87654321 0000FFFF FFFFBCDE
