Class Notes | Upload 7, Lecture notes of Digital Systems Design

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Class note

By Dr. Frank X. Li

ECEN 3733 Digital Circuit

Design

A 2-1 Mux

2 - 1 Mux Truth Table

A 4-1 Mux

7 Segment Decoder

What Decoder Does

How to build a 2-to-4 decoder?

8 bit Decoder

Programming ROM Example

Programming PROM, fixed AND and programmable OR Gates

Programmable Logic Array (PLA)

Programmable Logic Array (PLA), both OR & AND programmable

9500-series macrocell (18 per FB)

Xilinx CPLDs

Field Programmable Gate Arrays (FPGA)

• Historically, FPGA architectures and companies began around the same time as CPLDs
• FPGA is an IC that contains an array of identical logic cells with programmable interconnections
• FPGAs are closer to “programmable ASICs” -- large emphasis on interconnection routing - Timing is difficult to predict -- multiple hops vs. the fixed delay of a CPLD’s switch matrix. - But more “scalable” to large sizes.
• FPGA programmable logic blocks have only a few inputs and 1 or 2 flip-flops, but there are a lot more of them compared to the number of macrocells in a CPLD.

FPGA Example