Clocking Techniques - Sequential Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

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Sequential Logic Design

Lecture

• Agenda
  1. Timing
  2. Clocking Techniques
• Announcements
  1. n/a

Timing

• Pipelined Logic
  • we can break up the combinational logic delay by inserting registers between each level.
  • this reduces combinational logic delay, but we don't get the information right away

Latency - the time you need to wait for the data to come out of the pipeline

Activity - the percentage of time that the signals are switching. More activity means that the pipeline will continually output data and Latency is not a problem.

• if the signals are not very active (i.e, a transition here and there), then the pipeline overhead might not be worth it.

• Clocking
  • in a synchronous system, the clock is the trigger for all data movement & manipulation
  • the clock is assumed to arrive at the CLK inputs of each Flip-Flop at the same time
  • in reality, this is not the case. Physical factors create mismatches in when the clock arrives at each register input
  • this timing error is called "Clock Skew"
  • this can be caused by:

1. Trace mismatching
2. Process variation - traces are wider on one side = different RC
3. Power Supply Variation - clocks distributed using buffers are sensitive to power

• Clock Trees
  • an H-Tree is a technique to distribute clocks to all regions of a chip with equal delay
  • the rule is that each time an H is added to any end-node, an H is added at every other end-node.
  • this keeps the RC's the same for all paths

• Clock Buffering (Clock Repeating)
  • we can use S to see how the RC delay of traces scales
  • interconnect delay can be considerable and dominating in modern IC's

w t ⋅

R ∝ Resistance scales following : S 2

w

t h

h

w

h

C ∝ Capacitance scales following : 1

h t ⋅

τ int ∝ Delay scales following : S 2

Horrible!!!

OK

Horrible!!!

• Clock Buffering (Clock Repeating)
  • R & C delay is also proportional to the Length of a trace (L)

R = L·(ρ/t·w) C = L·(εr w/h) τint ∝ RC ∝ L 2

• this means there is a quadratic dependency between delay and trace length
• this is a major problem in clock trees w

t h

h

L

• Clock Buffering (Clock Repeating)
  • advantages of clock repeating:

1. linear scaling of delay with length
2. signal strength at end-node is good

• disadvantages of clock repeating

power consumption of active buffers