ECE 4110: Sequential Logic Design - Lecture 1, Slides of Digital Logic Design and Programming

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Sequential Logic Design

ECE 4110– Sequential Logic Design

Lecture

• Agenda
  1. Course Logistics
  2. Course Content
  3. Digital Review
• Announcements
  1. Welcome
  2. Homework #1 assigned

Course Overview

• Textbook: “Digital Design: Principles and Practices",

4th Addition

John F. Wakerly,

Prentice Hall, 2006

• Website: all handouts, homework assignments are

– it is your responsibility to download assignments

Course Overview

 Office Hours: 331 Brown Hall MWF, 8:00am – 9:00am Also available by email appointment  Pre-requisites: ECE2110 / ECE  Grading: Homework/VHDL and Quizzes 20% Combo System project 20% Exam #1 20% Exam #2 20% Final Exam 20%

• Homework Assignments are due at the beginning of class.
• No Late homework will be accepted.
• No make up exams will be given, unless pre-execuesd before the test. Plan on being available on the exam dates.
• Term paper assignment will be given for 5110 graduate level.

Course Overview

• Where does this course fit into the Computer Engineering curriculum?

Course Content

 What is this course?

• In ECE2110 you learned:
  • basic combinational logic design
  • basic sequential logic design
• In ECE3160 you learned:
  • how to implement logic circuits using off-the-shelf parts
• ECE4110 is a follow-on course that looks at:
  • Large scale digital designs
  • Performance of digital circuitry
  • Programmable Logic

Course Content

• We will learn VHDL in order to describe large digital designs

- VHDL is a text based Hardware Description Lang

- We can simulate our digital designs created in V

Course Content

• We can also prototype our designs using an FPGA

- FPGA = Field Programmable Gate Array

- An FPGA is a programmable logic device

- In this course,

• we will implement our designs and test them in FPGA hardware

Digital Review

Combinational Logic Combinational Logic Gates :

• Output depends on the logic value of the inputs
• no storage

Digital Review

NOT out = in’ = in f(in) = in’ = in OR out = a+b f(a,b) = a+b AND out = a·b f(a,b) = a·b

Digital Review

XNOR out = a⊕b f(a,b) = a⊕b Also remember about XOR Gates: f(a,b) = a⊕b = (a’b + b’a) Also remember the priority of logic operations (without parenthesis) is: NOT, AND, OR

Digital Review

DeMorgan’s Theorems

• Inverting the output of any gate results in the same function as the opposite gate (AND/OR) with inverted inputs

Digital Review

Boolean Expressions Using SOP

• Logic functions can be described using a Sum of Products techniques
• Sum of Products (SOP) is the summation of all minterms resulting in the truth table
• A minterm is the expression for an input configuration which yields a TRUE output
• A minterm expression is the AND’ing of the input "1" signal configuration SOP Expression : f(a,b) = a’·b + a·b’ Note : un-minimized Boolean expression Truth Table a b out 0 0 0 0 1 1 minterm m 1 = a’·b 1 0 1 minterm m 2 = a·b’ 1 1 0

Digital Review

Boolean Expressions Using POS

• Logic functions can be described using a Product of Sums techniques
• Product of Sums (POS) is the multiplication of all maxterms resulting in the truth table
• A maxterm is the expression for an input configuration which yields a FALSE output
• A maxterm expression is the OR’ing of the input "0" signal configuration POS Expression : f(a,b) = (a+b) · (a'+b') Truth Table a b out 0 0 0 maxterm m 0 = a+b (input configuration of 0's) 0 1 1 1 0 1 1 1 0 maxterm m 3 = a'+b' (input configuration of 0's)