Introduction to
CMOS VLSI
Design
Lecture 1:
Circuits & Layout
David Harris
Harvey Mudd College
Spring 2004
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Guidelines and tips
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
cmos (very large scale integration), Lecture notes of Very large scale integration (VLSI)
its actually a book of cmos and details of Vlsi
Typology: Lecture notes
2017/2018
1 / 54
This page cannot be seen from the preview
Don't miss anything!
Related documents
Partial preview of the text
Download cmos (very large scale integration) and more Lecture notes Very large scale integration (VLSI) in PDF only on Docsity!
Introduction to
CMOS VLSI
Design
Lecture 1:
Circuits & Layout
David Harris
Harvey Mudd College Spring 2004
Outline
q A Brief History q CMOS Gate Design q Pass Transistors q CMOS Latches & Flip-Flops q Standard Cell Layouts q Stick Diagrams
Annual Sales
q 1018 transistors manufactured in 2003
- 100 million for every human on the planet
0
50
100
150
200
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 Year
Global Semiconductor Billings (Billions of US$)
Invention of the Transistor
q Vacuum tubes ruled in first half of 20th^ century Large, expensive, power-hungry, unreliable q 1947: first point contact transistor
- John Bardeen and Walter Brattain at Bell Labs
- Read Crystal Fire By Riordan, Hoddeson
MOS Integrated Circuits
q 1970’s processes usually had only nMOS transistors
- Inexpensive, but consume power while idle
q 1980s-present: CMOS processes for low idle power
Intel 1101 256-bit SRAM Intel 4004 4-bit μProc
Moore’s Law
q 1965: Gordon Moore plotted transistor on each chip
- Fit straight line on semilog scale
- Transistor counts have doubled every 26 months
Year
Transistors
40048008 8080
8086
80286 Intel
Intel486 PentiumPentium Pro
Pentium IIPentium IIIPentium 4
1,
10,
100,
1,000,
10,000,
100,000,
1,000,000,
1970 1975 1980 1985 1990 1995 2000
Integration Levels SSI : 10 gates MSI : 1000 gates LSI : 10,000 gates VLSI : > 10k gates
CMOS Gate Design
q Activity:
- Sketch a 4-input CMOS NAND gate
CMOS Gate Design
q Activity:
- Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
Series and Parallel
q nMOS: 1 = ON q pMOS: 0 = ON q Series : both must be ON q Parallel : either can be ON
(a)
a b
a
b g2g1^0 0
a
b
0 1
a
b
1 0
a
b
1 1 OFF OFF OFF ON
(b)
a b
a
b
g1g2^0 0
a
b
0 1
a
b
1 0
a
b
1 1 ON OFF OFF OFF
(c)
a b
a b
g1 g2 (^0 ) OFF ON ON ON
(d) ON ON ON OFF
a b
0
a b
1
a b
1 0 1 1
a b
0 0
a b
0
a b
1
a b
1 0 1 1
a b
g1 g
Conduction Complement
q Complementary CMOS gates always produce 0 or 1 q Ex: NAND gate
- Series nMOS: Y=0 when both inputs are 1
- Thus Y=1 when either input is 0
- Requires parallel pMOS
q Rule of Conduction Complements
- Pull-up network is complement of pull-down
- Parallel -> series, series -> parallel
A B
Y
Example: O3AI
q Y = ( A + B + C )g D
Example: O3AI
q Y = ( A + B + C )g D
A B
Y
C
D
C D
B
A
Pass Transistors
q Transistors can be used as switches
g s d
g s d
Pass Transistors
q Transistors can be used as switches
g s d
g = 0 s d g = 1 s d
0 strong 0
Input Output
1 degraded 1
g s d
g = 0 s d g = 1 s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0