Code Generation and Debugging Tools - Introduction to Microprocessor Systems - Lecture Sli, Lecture notes of Computer Science

These are the Lecture Slides of Introduction to Microprocessor Systems which includes Microprocessor, Organization, Programming, Programming Language Characteristics, High Level Language, Assembly Language, Machine Language, Assembler Functions, Mnemonic etc. Key important points are: Code Generation and Debugging Tools, Microprocessor, Organization, Programming, Programming Language Characteristics, High Level Language, Assembly Language, Machine Language, Assembler Functions, Mnemonic

Typology: Lecture notes

2012/2013

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Topics
Code Generation and Debugging Tools
ARM7TDMI Microprocessor
Organization
Programming
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Topics

• Code Generation and Debugging Tools

• ARM7TDMI Microprocessor

– Organization

– Programming

Code Generation

• Programming Language Characteristics

– High-Level Language (HLL)

– Assembly Language

– Machine Language

• Assembler Functions

– What does an assembler do?

Code

Generation

Process –

Generic

EDITOR

ASSEMBLER

LINKER

LOCATOR

HEX Conversion

source file (*.s)

relocatable object file (*.o)

relocatable linked object file

absolute executable file (*.axf)

HEX-ASCII object file (*.hex)

DEVICE

PROGRAMMER

list file (*.lst)

linker map file (*.map)

locator map file (*.map)

programmed device

blank device

Other object files

from assembler

or HLL compilers

Code

Generation

Process –

ECE 353

and

ECE 315

EDITOR

ASSEMBLER

LINKER/ LOCATOR

ADuC Simulator

source file (*.s)

relocatable object file (*.o)

absolute executable file (*.axf)

ULink JTAG Pod

list file (*.lst)

map file (*.map)

Other object files

from assembler

or HLL compilers

ADuC Hardware

HEX conversion

Device Programmer

Source Code File

; Filename: sample.s

; Author: ECE 353 Staff

; Description: sample program for week 3 lecture

; do NOT use this as the basis for any programming!

EXPORT Reset_Handler ;make available to linker

IOPORT_ADDRESS EQU 0x

AREA Reset, CODE, READONLY ARM

Reset_Handler

LDR PC, aLoop ;jump absolute

Loop

LDR R0, aPort ;load address of port LDR R1, [R0] ;read switch state LSL R1, #8 ;shift left 8 bits to align MVN R1, R1 ;complement STR R1, [R0] ;write LEDs NOP ;do nothing B Loop ;repeat forever

aLoop DCD Loop

aPort DCD IOPORT_ADDRESS

END Docsity.com

Assembler Listing File (1)

4 00000000 ; do NOT use this as the basis for any programming! 5 00000000 6 00000000 EXPORT Reset_Handler ;make available t o linker 7 00000000 8 00000000 80001000 IOPORT_ADDRESS EQU 0x 9 00000000

10 00000000 AREA Reset, CODE, READONLY

11 00000000 ARM

12 00000000

13 00000000 Reset_Handler

14 00000000 E59FF018 LDR PC, aLoop

15 00000004 Loop

16 00000004 E59F0018 LDR R0, aPort ;load address of port

17 00000008 E5901000 LDR R1, [R0] ;read switch state

18 0000000C E1A01401 LSL R1, #8 ;shift left 8 bits

to align

19 00000010 E1E01001 MVN R1, R1 ;complement

20 00000014 E5801000 STR R1, [R0] ;write LEDs

21 00000018 E1A00000 NOP ;do nothing

22 0000001C EAFFFFF8 B Loop ;repeat forever

23 00000020

24 00000020 00000000

aLoop DCD Loop

25 00000024 80001000

aPort DCD IOPORT_ADDRESS

26 00000028

27 00000028 END

Assembler Listing File (3)

Symbol: aLoop

Definitions At line 24 in file sample.s Uses At line 14 in file sample.s

Comment: aLoop used once

aPort 00000024

Symbol: aPort

Definitions At line 25 in file sample.s Uses At line 16 in file sample.s

Comment: aPort used once

5 symbols

ARM Macro Assembler Page 1 Alphabetic symbol ordering

Absolute symbols

IOPORT_ADDRESS 80001000

Symbol: IOPORT_ADDRESS

Definitions At line 8 in file sample.s Uses At line 25 in file sample.s

Comment: IOPORT_ADDRESS used once

1 symbol

321 symbols in table

Disassembly Window

0x00080000 E59FF018 DD 0xE59FF

0x00080004 E59F0018 LDR R0,[PC,#0x0018]

0x00080008 E5901000 LDR R1,[R0]

0x0008000C E1A01401 MOV R1,R1,LSL #

0x00080010 E1E01001 MVN R1,R

0x00080014 E5801000 STR R1,[R0]

0x00080018 E1A00000 NOP

0x0008001C EAFFFFF8 B 0x

0x00080020 00080004 DD 0x

0x00080024 80001000 ANDHI R1,R0,R

0x00080028 00000000 ANDEQ R0,R0,R

0x0008002C 00000000 ANDEQ R0,R0,R

0x00080030 00000000 ANDEQ R0,R0,R

0x00080034 00000000 ANDEQ R0,R0,R

aPort

aLoop

B/BL{} <target_address>

RTL: PC  PC + (signed_immediate_24 << 2)

Linker Map File (2)

Image component sizes

Code (inc. data) RO Data RW Data ZI Data Debug Object Name

40 8 0 0 0 244 sample.o


40 8 0 0 0 244 Object Totals 0 0 0 0 0 0 (incl. Generated) 0 0 0 0 0 0 (incl. Padding)


0 0 0 0 0 0 Library Totals 0 0 0 0 0 0 (incl. Padding)


================================================================================

Code (inc. data) RO Data RW Data ZI Data Debug

40 8 0 0 0 244 Grand Totals 40 8 0 0 0 244 Image Totals

================================================================================

Total RO Size (Code + RO Data) 40 ( 0.04kB) Total RW Size (RW Data + ZI Data) 0 ( 0.00kB) Total ROM Size (Code + RO Data + RW Data) 40 ( 0.04kB)

================================================================================

Hex Record Format

:0400000500080000EF

:020000040008F

:1000000018F09FE518009FE5001090E50114A0E1AD

:100010000110E0E1001080E50000A0E1F8FFFFEA

:0800200004000800001000803C

:00000001FF

Record

Mark

Record Length

Load Address or 0000

Record Type

Data Checksum Record Description

: 04 0000 05 00080000 EF Start linear address record

: 02 0000 04 0008 F2 Extended linear address record

: 10 0000 00 18F09FE518009FE

001090E50114A0E

AD Data record

: 10 0010 00 0110E0E1001080E 0000A0E1F8FFFFEA

38 Data record

: 08 0020 00 0400080000100080 3C Data record

: 00 0000 01 FF End-of-file record

Simulator

Runs on a host computer, and simulates execution

of your code. No actual hardware required.

Strengths

Weaknesses

Native Debugger

Code is executed on a host computer with a

compatible instruction set.

Strengths

Weaknesses

Remote Debugger

Similar to resident monitor, but only small

debugger kernel on UUT. Main debugger software

runs on a host computer connected to the UUT.

Strengths

Weaknesses

In-Circuit Emulator (ICE)

Replaces UUT CPU with hardware that gives full control of

CPU pins (i.e. can run arbitrary bus cycles). Often contain

overlay memory to allow testing of software before system

hardware is available. May clamp over existing CPU that is

soldered in place.

Strengths

Weaknesses