External Memory Interface - Introduction to Microprocessor Systems - Lecture Sli, Lecture notes of Computer Science

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Topics

• ADuC7026 External Memory Interface
  • Implementation
  • Demultipexing
• Bus Timing
  • Bus cycle timing modification
    • Wait states and more
• Assessing timing compatibility

Basic System Bus Operation

• Address
  • Unidirectional from CPU
• Data
  • Bidirectional
• Control
  • /RS or /RD – output from CPU
    • Indicates a read operation in progress
  • /WS or /WR – output from CPU
    • Indicates a write operation in progress
  • /WAIT or /READY – input to CPU
    • Used by external device to signal that it is not able to complete transfer yet (not present on ADuC7026) Docsity.com

Basic Read Cycle at Bus Level

Basic Write Cycle at Bus Level

16-Bit Memory System

SRAM Timing Compatibility

• In order to properly read and write the

device, we need to ensure that the

processor-to-memory interface is compatible

with the memory device.

• This is accomplished by analyzing the timing

for all relevant parameters, and ensuring

that the operation can be completed

successfully.

• We will work through the read cycle analysis

for the ADuC7026... Docsity.com

Basic Read Cycle at Bus Level

Read Cycle Controls

tAA – address access time

tACS – chip enable to valid data

tDF – output hold/float time

ADuC7026 External Memory Interface Configuration

• The external memory interface supports four

independently configured memory regions,

each of which is 128kB in size.

• In order to use the external memory interface,

we need to

• Configure the required pins (GPxCON)
• Enable the external interface (XMCFG[0] = 1)
• Region enable and bus width (XMxCON)
• Configure region for the desired bus timing (XMxPAR)

ADuC7026 XMxPAR

• The XMxPAR MMR configures the bus timing for a region - 0x70FF at reset
• [14:12] – AE extend
• [9] – implements bus turn-around
• [8] – provides additional hold time
• [7:4],[3:0] – extend write/read strobes

Write cycle timing control Read cycle timing control

System Timing Compatibility

• Consider again the system.
• Analyzing write cycle timing.
• SRAM write characteristics
  • tWC
  • tAS , tAW, tCW
  • tWR
  • tWDS , tWDH
  • Write cycle controls