COEN 317 - Microprocessor-based Systems Assignment 2, Assignments of Computer Science

1. Consider a subtraction instruction with flexible second operand Operand2: SUB Rd, Rn, Rm, LSL #n It is desired to modify this instruction to the following new syntax: SUB Rd, Rm, LSL #n, Rn This new syntax can be called subtraction instruction with flexible first operand Operand1. What minimum change in the hardware architecture is required for the implementation of this instruction? Please draw hardware modifications. (10 points) Microprocessor-based Systems โ€“ Assignment 2 Solution 1: A shifter must be added between the first operand and the ALU input. The first operand is given to the shift unit before passing to the ALU as an input.

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COEN 317 - Microprocessor-based Systems
Assignment 2
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COEN 317 - Microprocessor-based Systems

Assignment 2

1. Consider a subtraction instruction with flexible second operand Operand 2 : SUB Rd, Rn, Rm, LSL #n It is desired to modify this instruction to the following new syntax: SUB Rd, Rm, LSL #n, Rn This new syntax can be called subtraction instruction with flexible first operand Operand 1. What minimum change in the hardware architecture is required for the implementation of this instruction? Please draw hardware modifications. ( 10 points)

Solution 1 :

A shifter must be added between the first operand and the ALU input. The first operand is given to the shift unit before passing to the ALU as an input. ALU Register Bank Read reg Write reg Read reg Operand 1 Operand 2 Shifter

Solution 2 :

To code 64 instructions, 6 bits are required ( 64 = 2 6 ). Therefore, opcode (instruction) field must be 6 bits. a) Since the first 6 registers are available in this case ( 2 2 = 4 , so 2 is not enough), 3 bits are required for register addressing. There are two fields for registers: Rds, and Rs. Therefore 6 bits are needed for these two. The last field is imm, which can have 16 โˆ’ 6 โˆ’ 6 = 4 bits. It means that 4 bits will be available for the immediate register. b) Since all 32 registers are available in this case ( 2 5 = 32 ), Rs 1 field = Rs 2 field = Rds field = 5 bits. Instruction = 6 bits, and imm = 32 โˆ’ 5 โˆ’ 5 โˆ’ 5 โˆ’ 6 = 11 bits for the immediate field c) Like the previous part, Rs = 5 bits, Rds = 5 bits. Instruction = 6 bits, and imm = 32 โˆ’ 5 โˆ’ 5 โˆ’ 6 = 16 bits.

3. Consider the execution of an addition instruction. Before the execution of this instruction, both C and V flags are cleared. If the instruction uses the S suffix, then give two examples of operands that result in the setting of C and V flags: One example of operands that results in the setting of the C flag, and another example of operands that results in the setting of the V flag. ( 8 points)

Solution 3 :

Carry flag will be set when there is a carry after an arithmetic instruction such as addition. Assume R 1 = AB 00 0000 and R 2 = A 200 0000. Then ADD R 1 , R 2 results in a carry, therefore carry flag will be set to 1.

4. Write the equivalent assembly instructions for each of the following instructions written in C (programming language). Assume ๐‘ฅ, ๐‘ฆ, and ๐‘ง are R 1 , R 2 , and R 3 registers, respectively. ( 12 points) a) ๐‘ฆ = ๐‘ง + ๐‘ฅ/ 32 ; b) ๐‘ง = โˆ’ 1 โˆ— ๐‘ง + ๐‘ฆ โˆ— ๐‘ฅ;

Solution 4 :

a) ADD R 2 , R 3 , R 1 , ASR # 5 b) MLS R 3 , R 2 , R 1 , R 3 or (both are equivalent) MLS R 3 , R 1 , R 2 , R 3

5. Assume the content of the registers and flags are as follows before executing any instructions (values are signed): R 1 = A 000 D 4 BA H R 2 = B 001 B 1 C 2 H R 3 = 7 FFF FFFE H R 4 = 8000 0002 H N = 0 , Z = 0 , C = 1 , V = 0 , Q = 0 Indicate the content of registers and flags after executing each one of the following instructions: ( 30 points) a) ADD R 1 , R 2 b) ADD R 3 , R 1 , R 2 c) ADDS R 1 , R 2 d) ADDS R 3 , R 4 , R 3 e) ADCS R 3 , R 1 , R 2 f) ADDEQ R 3 , R 4 Note: Examine each instruction independent of the previous instructions.

Solution 5 (continue):

d) ADDS R 3 , R 4 , R 3 : The flags are updated. e) ADCS R 3 , R 1 , R 2 : This one is an addition with carry. Since carry bit is 1 , the result of R 1 , and R 2 addition will be incremented by 1. f) ADDEQ R 3 , R 4 : This one is a conditional instruction. EQ means if zero flag is equal to 1 (i.e. Z = 1 ), then execute the instruction. Since before this instruction execution Z = 0 , therefore the instruction will not be executed, and everything will remain unchanged.

R1 R2 R3 R4 N Z C V Q

A000 D4BA B001 B1C2 0000 0000 8000 0002 0 1 1 0 0

R1 R2 R3 R4 N Z C V Q

A000 D4BA B001 B1C2 5002 867D 8000 0002 0 0 1 1 0

R1 R2 R3 R4 N Z C V Q

A000 D4BA B001 B1C2 7FFF FFFE 8000 0002 0 0 1 0 0

6. Consider the following assembly program: ( 16 points) MOV CX, 1100 H DLY: SUBS CX, CX, # 1 NOP BNE DLY NXT: --- --- (a) How many times does the BNE DLY instruction get executed? (b) Change the program so that BNE DLY is executed 22 times.

Solution 6 :

The program is known as the delay loop: a) 110016 = 2 12

  • 2 8 = 4352 times b) 22 = 1616 โ†’ 1100 H must be replaced with 16 H