L16- Building a Computer 1
Comp 411 – Fall 2007 10/24/07
Building a Computer
I wonder where
this goes?
Instruction
Memory
A
D
01
MIPS Kit
ALU
AB
Quiz #2 on 10/31, open book and notes
(This is the last lecture covered)
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MIPS Assembly Instruction Set and Implementation - Comp 411 Fall 2007 - Prof. Leona Mcmill, Study notes of Computer Architecture and Organization
An overview of the mips assembly instruction set, its implementation, and various instruction examples. Instruction classes such as i-type, j-type, r-type, and their functions. It also discusses flags, instruction fetch/decode, and the 3-operand alu data path.
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L16- Building a Computer 1
Building a Computer
I wonder wherethis goes?
(^0) InstructionMemory A^1 D
MIPS Kit
A^ ALUB
Quiz #2 on 10/31, open book and notes(This is the last lecture covered)
L16- Building a Computer 2
THIS IS IT!
“Motivating Force”
or “Inciting Incident” This is the point in the coursewhere the PLOT actually begins.We are now ready to build acomputer.The ingredients are all in place,now it is time to build a legitimatecomputer. One that executesinstructions, much the way anyother desktop, PDA, or othercomputer does.
L16- Building a Computer 4
Design Approach
Each instruction class can be implemented using a simple componentrepertoire. We’ll try implementing data paths for each class individually,and merge them (using MUXes, etc).Steps:1. 3-Operand ALU instructions2. ALU w/immediate
instructions2. Load & Store Instructions3. Jump & Branch instructions4. Exceptions5. Merge data paths
Our Bag of Components:
Registers
(^1 )
Muxes
A^ B^ ALU
ALU & adders
WDA^ DataMemoryRDR/W
RA1^ RA2WA^ RegisterWEFile(3-port)WD RD1^ RD
A^ InstructionMemoryD Memories
Incremental Featurism
L16- Building a Computer 5
A Few ALU Tweaks
Let’s review the ALU that we built a few lectures ago.
(With a few minor additions)
A^ FlagsV,C
B
BidirectionalBarrelShifter^ R
Boolean
Add/Sub
Sub Bool ShftMath
N Flag
Z Flag
Sub Bool Shft Math
OP 0 XX^
0 1
A+B 1 XX^
0 1
A-B X^ X^
1 1
0
X^ X^
1 1
1
X^00
1
0 B<<A X^10
1 0
B>>A X^ 1 1^
1 0
B>>>A X^00
0
0 A & B X^01
0 0
A | B X^10
0 0
A ^ B X^ 1 1^
0 0
A | B
5-bit ALUFN
L16- Building a Computer 7
3-Operand ALU Data Path
RA1^ RegisterFile
RA
RD^
RD
WA^
WDWE
Rd: <15:11>
PC +
Instruction AMemoryD
Rt: <20:16> ALU A^
B
ALUFN
Control LogicALUFN^ WERF
WERF
00
000000 Rs: <25:21>
r s^
rt^
rd^
100XXX 00000
R-type:
ALU with Reguster operandsReg[rd]
←←←←^ Reg[rs] op Reg[rt]
WERF!
L16- Building a Computer 8
Shift Instructions
RA1^ RegisterFile
RA
RD^
RD
WA^
WDWE
Rd: <15:11>
PC +
Instruction AMemoryD
Rt: <20:16>
A^ ALU
B
ALUFN
Control LogicALUFN^ WERF
WERF
00
r s^
rt^
rd^
000XXX shamt
R-type:
ALU with Reguster operandssll: Reg[rd]
←←←←^ Reg[rt] (shift) shamt
sllv: Reg[rd]
←←←←^ Reg[rt] (shift) Reg[rs]
ASEL
Rs: <25:21>
shamt:<10:6>^ ASEL^10
ASEL!
L16- Building a Computer 10
Load Instruction
WA
PC +
Instruction AMemoryD
RA1^ RegisterFile
RA
RD^
RD
A^ ALU
B
WA^
WDWE
ALUFN
Control Logic
Imm: <15:0>
WD Data Memory RD
R/W
Adr
Wr
0 1 2 WDSEL
BSEL WDSEL ALUFN Wr
WERF
WERF
00
Rd:<15:11> Rt:<20:16>
BSEL^01
SEXT
r s
rt^
immediate
I-type:
LoadReg[rt]
←←←←^ Mem[Reg[rs] + SEXT(immediate)]
ASEL
Rt: <20:16>
Rs: <25:21>^ SEXT
BSEL 01
SEXT shamt:<10:6>^ ASEL^10
L16- Building a Computer 11
Store Instruction
WA
PC +
Instruction AMemoryD
RA1^ RegisterFile
RA
RD^
RD
A^ ALU
B
WA^
WDWE
ALUFN
Control Logic
Imm: <15:0>
WD Data Memory RD
R/W
Adr
Wr
0 1 2 WDSEL
BSEL WDSEL ALUFN Wr
WERF
WERF
00
Rd:<15:11> Rt:<20:16>
SEXT ASEL
10X
r s
rt^
immediate
I-type:
StoreMem[Reg[rs] + SEXT(immediate)]
←←←←^ Reg[rt]
Rt: <20:16>
BSEL
No WERF!
Rs: <25:21>^ SEXT^ ASEL^10
BSEL 01
SEXT shamt:<10:6>
L16- Building a Computer 13
BEQ/BNE Instructions
WA
PC +
Instruction AMemoryD
RA1^ RegisterFile
RA
RD^
RD
A^ ALU
B
WA^
WDWE
ALUFN
Control Logic
WD Data Memory RD
R/W
Adr
Wr
0 1 2 WDSEL
J:<25:0>^ PCSEL^ BSEL^ WDSEL^ ALUFN^ Wr
WERF
WERF
00
PC+
Rt: <20:16>
10X011^ Imm: <15:0> SEXT ASEL
immediate
rs^
rt
R-type:
Branch Instructionsif (Reg[rs] == Reg[rt]) PC
←←←←^ PC + 4 + 4*SEXT(immediate)
if (Reg[rs] != Reg[rt]) PC
←←←←^ PC + 4 + 4*SEXT(immediate)
x4 + BT
Z
Z
BT
PC<31:29>:J<25:0>:
That “x4” unit istrivial. I’ll just wirethe input shiftedover 2–bitpositions. Why add, anotheradder? Couldn’t wereuse the one inthe ALU? Nope, itneeds to do asubtraction.
WASEL
Rs: <25:21>^ SEXT^ ASEL^10
BSEL 01
SEXT shamt:<10:6>
PCSEL^
(^012) (^345) 6
WASEL
Rd:<15:11> Rt:<20:16>^
(^01) “31” (^2) “27” 3
L16- Building a Computer 14
Jump Indirect Instructions
WA
PC +
Instruction AMemoryD
RA1^ RegisterFile
RA
RD^
RD
A^ ALU
B
WA^
WDWE
ALUFN
Control Logic
WD Data Memory RD
R/W
Adr
Wr
0 1 2 WDSEL
J:<25:0>^ PCSEL^ BSEL^ WDSEL^ ALUFN^ Wr
WERF
WERF
00
PC+
Rt: <20:16>
R-type:^ Imm: <15:0> SEXT ASEL
Jump Indirect, Jump and Link Indirectjr:^ PC
←←←←^ Reg[rs]
jalr:^ PC
←←←←^ Reg[rs], Reg[rd]
←←←←^ PC + 4
x4 + BT
Z
Z
BT
WASEL
PC<31:29>:J<25:0>:
r s^
rt^
rd^
00100X
00000
JT
JT
Rs: <25:21>^ SEXT^ ASEL^10
BSEL 01
SEXT shamt:<10:6>
PCSEL^
(^012) (^345) 6
WASEL
Rd:<15:11> Rt:<20:16>^
(^01) “31” (^2) “27” 3
L16- Building a Computer 16
More Loose Ends
WA
PC +
Instruction AMemoryD
RA1^ RegisterFile
RA
RD^
RD
A^ ALU
B
WA^
WDWE
ALUFN
Control Logic
WD Data Memory RD
R/W
Adr
Wr
0 1 2 WDSEL
J:<25:0>^ PCSEL^ BSEL^ WDSEL^ ALUFN^ Wr
WERF
WERF
00
PC+
Rt: <20:16>
R-type: set on less than & set on less than unsignedImm: <15:0> SEXT ASEL
slt:^ if (Reg[rs] < Reg[rt]) Reg[rd]
←←←←^ 1; else Reg[rd]
←←←←^0
sltu: if (Reg[rs] < Reg[rt]) Reg[rd]
←←^ 1; else Reg[rd]←←
←←^0 ←←
x4 + BT
Z
BT
WASEL
PC<31:29>:J<25:0>:
JT
JT
r s^
rt^
rd^
10101X
00000
N^ V^ C
Rs:<25:21>^ SEXT^ ASEL^10 ZVN C
BSEL 01
SEXT shamt:<10:6>
PCSEL^
(^012) (^345) 6
WASEL
Rd:<15:11> Rt:<20:16>^
(^01) “31” (^2) “27” 3
L16- Building a Computer 17
LUI Ends
WA
PC +
Instruction AMemoryD
RA1^ RegisterFile
RA
RD^
RD
A^ ALU
B
WA^
WDWE
ALUFN
Control Logic
WD Data Memory RD
R/W
Adr
Wr
0 1 2 WDSEL
J:<25:0>^ PCSEL^ BSEL^ WDSEL^ ALUFN^ Wr
WERF
WERF
00
PC+
Rt: <20:16>
I-type: Load upper immediateImm: <15:0> SEXT ASEL
lui:^ Reg[rt]
←←←←^ Immediate << 16
x4 + BT
Z
BT
WASEL
PC<31:29>:J<25:0>:
JT
JT
N^ V^ C
ZVN C
001XXX
immediate
r t Rs:<25:21>^ SEXT
BSEL (^01) SEXT
PCSEL^
(^012) (^345) 6
WASEL
Rd:<15:11> Rt:<20:16>^
(^01) “31” (^2) “27” 3 shamt:<10:6>^ “16”^ ASEL^201
L16- Building a Computer 19
Exceptions
WA
PC +
Instruction AMemoryD
RA1^ RegisterFile
RA
RD^
RD
A^ ALU
B
WA^
WDWE
ALUFN
Control Logic
WD Data Memory RD
R/W
Adr
Wr
0 1 2 WDSEL
J:<25:0>^ PCSEL^ BSEL^ WDSEL^ ALUFN^ Wr
WERF
WERF
00
PC+
Rt: <20:16>
Imm: <15:0>^ + SEXT ASEL
x4 BT
Z
BT
WASEL
PC<31:29>:J<25:0>:
JT
JT
N^ V^ C
Rs:<25:21>^ SEXT^ ZVN C
BSEL (^01) SEXT
PCSEL^
(^012) (^345) 6
IRQ^ LSEL
0x800000000x80000040 0x
RESET
IRQ:^
Reg[27]
←^ PC+4; PC
←^ 0x
Bad Opcode:
Reg[27]
←^ PC+4; PC
←^ 0x
Reset:
PC^ ←^ 0x
These inputsshouldprobably beregistered afew times toavoidmetastabilityproblems
shamt:<10:6>“16”^ ASEL^201 WASEL Rd:<15:11> Rt:<20:16>^
(^01) “31” (^2) “27” 3
L16- Building a Computer 20
MIPS: Our Final Version
This is a complete 32-bit processor.Although designed in one class lecture,it executes the majority of theMIPS R2000 instruction set.
• Executesoneinstructionper clock • All that’sleft is thecontrollogicdesign
WA
PC +
Instruction AMemoryD
RA1^ RegisterFile
RA
RD^
RD
A^ ALU
B
WA^
WDWE
ALUFN
Control Logic
WD Data Memory RD
R/W
Adr
Wr
0 1 2 WDSEL
J:<25:0>^ PCSEL^ BSEL^ WDSEL^ ALUFN^ Wr
WERF
WERF
00
PC+
Rt: <20:16>
Imm: <15:0>^ + SEXT ASEL
x4 BT
Z
BT
WASEL
Rd:<15:11> Rt:<20:16>^
0123
WASEL
PC<31:29>:J<25:0>:
JT
JT
N^ V^ C
Rs: <25:21>^ SEXT^ ASEL^20 ZVN^ C
BSEL (^01) SEXT shamt:<10:6>
PCSEL^
(^012) (^345) 6
“16”
IRQ
0x800000000x80000040 0x
RESET
“31”“27”
1