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CS61C FINAL EXAM: EARLY VERSION, 5/11/
Last name ______________________ First name___________________________ Student ID number _______________ Login: cs61c-_______
Please circle the last two letters of your login name.
a b c d e f g h i j k l m n o p q r s t u v w x y z a b c d e f g h i j k l m n o p q r s t u v w x y z
Discussion section meeting time___________ TA's name __________________________ The student on my left is __________________________ login cs61c-_________ The student on my right is __________________________ login cs61c-_________
You are allowed to use two 8.5” x 11” double-sided handwritten pages of notes. No calculators. This booklet contains 11 numbered pages including the cover page, plus photocopied pages from COD and an ASCII table. Put all answers on these pages , please; don't hand in stray pieces of paper. The exam contains 9 substantive questions, plus the dreaded question 0 and the extra credit question. You have three hours, so relax – this exam isn’t worth having a heart failure over. Good luck!
I certify that my answers to this exam are all my own work. If I am taking this exam early, I certify that I shall not discuss the exam questions or answers with anyone until after the scheduled exam time.
Signature ________________________________________________________________
Question Max Points Your Points
The Dreaded Question 0 (-1 to 0)
Performance 7
Pliable Data, The Revenge 6
Theme and Variations 3
Cache and VM 6
The Newsgroup Question 11
HLL to Asm 12
Dave’s Dirty Clothes 6
Interrupt Questions 4
Tree Monkey Question 15
Extra Credit (+1)
Total 70
(If you are feeling down, starting the test by reading the Extra Credit question might help to inspire you !)
Question 0 (-1 point if not followed): Fill out the front page correctly and write your login at the top of each of the pages. Circle your login initials on the cover page so that we can read them.
Performance Question (7 points):
You are running a benchmark on your company's processor, Mbase , which runs at 400 MHz and has the following characteristics:
Instruction Type Frequency Cycles A 40% 2 B 30% 3 C 20% 3 D 10% 5
a) (2 points) What is the CPI rating for Mbase?
You ask the hardware team if they can improve the processor design. They tell you that they could make this processor run at 500 MHz, however they would have to increase the number of cycles for instruction type C to 4. (All the other instruction types still take the same number of cycles). Call this machine Mopt.
Instruction Type Frequency Cycles A 40% 2 B 30% 3 C 20% 4 D 10% 5
b) (1 point) What is the CPI rating for Mopt?
c) (2 points) How much faster is Mopt than Mbase (you may leave the answer as an improper fraction)?
d) (2 points) Is there an instruction mix that makes Mbase faster than Mopt? If so, suggest such a mix. (Note: The mix doesn’t have to contain all the instruction types.)
Mbase:
Mopt:
Theme and Variations (3 points):
Match the C expressions on the left with the logic circuits on the right.
Question 1
Output = 0
A
Output
X
Y
Question 2
Output = (X && !Y) || (Y && !X)
B
X
Y
Output
Question 3
Output = (X && Y)
C
Write your answers here:
1. ______ 2. ______ 3. ______
Cache and VM Question (6 points):
The page size of a computer is 16 Kbytes ; the block size is 32 words and the machine is byte -addressable. The cache size is 1 Kbtye , and it is 4-way set associative. The virtual addresses are 42 bits and physical addresses are 36 bits long. Calculate the sizes (number of bits) of the following fields:
a) block offset ________
b) set index ________
c) tag ________
d) page offset ________
e) virtual page number ________
f) physical page number ________
The Newsgroup Question (11 points):
Although the CS61C review lecture on variable arguments was great, Joe Computer is very puzzled. What is this M'Piero thing? What does it have to do with Kelvin? "I don't get it!" Determined to find the answer to his confusion, he decides to check the newsgroup by starting the program "trn."
In what order do things happen when trn is run? Part 1 lists a set of things that occur when trn is run. Please time-order the steps from 1 to 13. The odd numbered steps are given to you. Fill in the rest with even numbers.
Please assume:
- No part of the program has been loaded into memory yet.
- Page size is 4KB and there is only one cache.
- The page table entry loaded from the memory for page 0x00040 maps to physical page 0x14329.
- The TLB is between the CPU and the cache, as in class (the cache uses physical addresses).
- Block size for the cache is 8 words (32 bytes).
- In part 1 all of the actions occur. In part 2, some of them are incorrect and do not occur.
Part 1 (6 points):
Given steps:
1 Joe Computer types "trn" at the command line.
3 The CPU attempts to fetch the first instruction, 0x00040000 (pointed to by the pc).
5 The page table for this process is accessed to find the entry for address 0x00040000, which has the invalid bit set (not loaded from disk yet).
7 The TLB is updated with an entry mapping virtual page 0x00040 to physical page 0x14329, with the valid bit set.
9 The cache misses for the block containing 0x14329000 and attempts to load the block from memory.
11_ The instruction at virtual address 0x00040000 is successfully loaded from the cache, completing the instruction fetch phase.
13_ The CPU attempts to fetch the second instruction, 0x00040004.
Unordered steps: (Assign the even step numbers 2, 4, 6, 8, 10, and 12 to the six options below)
_____ The TLB hits for virtual page number 0x00040, the physical address 0x14329000 is sent to the cache.
_____ The TLB misses while attempting to find an entry for the virtual page number 0x00040.
_____ Physical page number 0x14329 is loaded into memory from disk, and the page table is updated.
_____ The instruction at virtual address 0x00040000 is successfully fetched, and on the next clock tick will move on to its decode stage.
_____ A page table for the process is created by the operating system. Static memory area is created, space is allocated for the static parts (i.e. arrays) of the program, heap and stack are initialized. All the TLB entries from the previous process are marked invalid.
_____ The block containing 0x14329000 is loaded into the cache from memory.
HLL to Asm Question (12 points):
Below are four pieces of C code and four pieces of MIPS code. In the blank provided next to each piece of C code, enter the letter corresponding to the MIPS code that accurately performs EXACTLY the same function as the C code. Each piece of MIPS code matches to exactly one and only one piece of C code. There are no repeats. There are no “none of the above” answers.
Assume that, at the beginning of each piece of C code, the integer variable i contains as its value a non-negative integer. Also assume that both arrays are integer arrays of size 20 (so there will be no addressing problems in any of the code).
Let the following be true of the registers prior to execution of the MIPS code: $t0 contains the value the integer variable i would contain in the corresponding C code $s0 contains the address of A[0] $s1 contains the address of B[0]
C code:
MIPS code:
D.
Begin: slti $t1, $t0, 10 beq $t1, $0, Fin sll $t1, $t0, 2 add $t2, $s1, $t lw $t3, 0($t2) add $t3, $t3, $t add $t2, $s0, $t sw $t3, 0($t2) addi $t0, $t0, 1 Fin:
C.
Begin: sll $t1, $t0, 2 add $t2, $s1, $t lw $t3, 0($t2) add $t3, $t3, $t add $t2, $s0, $t sw $t3, 0($t2) addi $t0, $t0, 1 slti $t1, $t0, 10 beq $t1, $0, Fin j Begin Fin:
B.
Begin: slti $t1, $t0, 10 beq $t1, $0, Fin sll $t1, $t0, 2 add $t2, $s1, $t lw $t3, 0($t2) add $t3, $t3, $t add $t2, $s0, $t sw $t3, 0($t2) j Begin Fin:
A.
Begin: slti $t1, $t0, 10 beq $t1, $0, Fin sll $t1, $t0, 2 add $t2, $s1, $t lw $t3, 0($t2) add $t3, $t3, $t add $t2, $s0, $t sw $t3, 0($t2) addi $t0, $t0, 1 j Begin Fin:
4. _____
for ( ; i <= 9; i++) { A[i] = B[i] + i; }
3. _____
if (i < 10) { A[i] = B[i]; A[i] += i; i++; }
2. _____
while (i < 10) { A[i] = B[i]; A[i] += i; }
1. _____
do { A[i] = B[i] + i; i++; } while (i < 10);
Dave’s Dirty Clothes Question (6 points):
The pipeline example in the book and in class used 5 stages (instruction fetch, instruction decode/register read, execute, data memory, and write back), and the time per stage was 2 ns for memory access, 2 ns for ALU operation, and 1 ns for register file read or write. Suppose we now replace the ALU with a faster version that runs in 1 ns, and we change the instruction cache and data cache so that they can accept a new address every 1 ns, but it still takes 2 ns to access the instruction or data. (The latency is still 2 ns, but throughput is one word every 1 ns.) The time for the rest of the stages is unchanged. Our new pipeline has 7 stages, as follows:
- Instruction Fetch Part A (start fetching next instruction)
- Instruction Fetch Part B (finish fetching next instruction)
- Instruction decode/register read/perform branch
- Execute
- Data Access Part A (start reading or writing desired data)
- Data Access Part B (finish reading or writing desired data)
- Write Back
This would look something like:
Select all of the following statements that are true about these two pipeline organizations. (Circle the letter if the statement is true, leave it unmarked otherwise).
a. The original pipeline could have a clock rate of 500 MHz, and the new pipeline could have a clock rate of 1000 MHz.
b. The peak instruction throughput is much improved in the new pipeline, but the instruction latency is unchanged.
c. If the old pipeline stalled for one clock cycle on an instruction dependent on a load, the new pipeline would have to stall for up to two clock cycles on an instruction dependent on a load.
d. If the old pipeline used a delayed branch mechanism (with one branch delay slot), the new pipeline would have a delayed branch mechanism with two branch delay slots.
Interrupt Questions (4 points):
Circle T or F:
T or F: When an exception or I/O interrupt occurs, interrupts are disabled while vital information is being saved.
T or F: Both add and addu can overflow. The only difference is that addu doesn't trigger an exception.
T or F: The instructions, lw and sw, do not trigger exceptions or I/O interrupts.
T or F: In order for an I/O interrupt to occur (for example when a key on the keyboard is pressed), the only bit that needs to be set is the device's I.E., found in one of its registers.
IF1 IF2 Dec Exc MA1 MA2 WB
IF1 IF2 Dec Exc MA1 MA2 WB
IF1 IF2 Dec Exc MA1 MA2 WB
[Tree Monkey Question continued]
(Fill in the code for CountBananas here.)
CountBananas:
Extra Credit Question (+1 point):
“Nothing in this world can take the place of persistence. Talent will not; nothing is more common than unsuccessful men with talent. Genius will not; unrewarded genius is almost a proverb. Education alone will not; the world is full of educated derelicts. Persistence and determination alone are omnipotent.”
Question: Who is credited with this quote?
