Download CS61C Midterm Exam Questions from UC Berkeley - EECS Department and more Exams Structural Analysis in PDF only on Docsity!
University of California, Berkeley – College of Engineering
Department of Electrical Engineering and Computer Science Spring 2004 Instructor: Dan Garcia 2004-05-
CS61C Final
Last Name First Name Student ID Number Login cs61c- The name of your TA (please circle) Alex Chema Jeremy Paul Roy Name of the person to your Left Name of the person to your Right All the work is my own. I had no prior knowledge of the exam contents nor will I share the contents with others in CS61C who have not taken it yet. (please sign)
Instructions
You are allowed to use two 8.5" x 11" double-sided handwritten pages of notes. No calculators are allowed. This booklet contains questions M0-M4 and F1-F5 on 10 numbered pages (including the cover page) and 3 duplicated pages from P&H and K&R. Write all your answers on this exam; show all work and do not hand in other pieces of paper. Question M0 (+1 points if correct) involves filling in the front of this page and putting your name & login on every sheet of paper. You have 3 hours to complete the exam. Good skill!
Problem M0 M1 M2 M3 M4 Total
Minutes 0 15 15 15 15 60
Max Score 1 11 11 11 11 45
Your Score
Problem F1 F2 F3 F4 F5 Total
Minutes 24 24 24 24 24 120
Max Score 18 18 18 18 18 90
Your Score
Overall Final Exam Score:
Question M1: Numbers (11 Points – 15 minutes)
a) In two's complement addition, how many of the 16 possible combinations of inputs to a 2-bit adder result in overflow? Assume no carry in. (3 points) b) We’re going to use a nibble (4 bits) to represent a floating point number as follows: SEEM ( bit for Sign, 2 for Exponent, 1 for Mantissa), with bias=1. We’ll follow the IEEE standard to reserve the smallest exponent for 0 & denorms (assume implicit exponent = 0), and the largest for NANs and ± ∞. Fill in the table below: (8 points) Description Number that the floating point notation on the right represents (in Decimal) Binary representation of the floating point notation (in Hex) Most negative # (that is not -∞) Zero 0 0x Smallest positive # Next-smallest positive #
Question M3: C (11 Points – 15 minutes)
You are called upon to find the bugs and predict the output of the following program that was typed into a PC word processor, like notepad or textedit, so we can’t trust the indenting. Specify actual or potential errors (not warnings) at compile-time (e.g., syntax) or run-time (e.g., out-of-bounds access) for lines (a)-(d). Concisely state your reasons (and suggest a fix) for all errors you find. Finally, give the output of line (e), assuming the compiler and the system ignores all the errors it finds. (2 pts each) struct dlist { int value; struct dlist *next; }; int main() { struct dlist **p; int i,j; p = (struct dlist **) malloc (10 * sizeof(float )); / line (a) / for (i=0; i<10; i++) (p+i) = (struct dlist ) malloc (20sizeof(struct dlist)); / line (b) / for (i=0;i<10; i++) { for(j=0; j<20; j++) { if(j<19) p[i][j].next = (p[i][j+1]); / line (c) / ((p+i)+j+1)->value = ij; / line (d) / } } printf("%d",p[5][15].value); / line (e) */ return 0; } Line Error? Circle “NO” or “CT” (for compile-time) or “RT” (for run-time) If it is an error, briefly state the reason (and suggest a fix) (a) (^) NO CT RT (b) (^) NO CT RT (c) (^) NO CT RT (d) (^) NO CT RT What is printed by line (e) (assume the compiler & system ignores all the errors it finds )? ______
Name: _______________________________ Login: cs61c-____
Question M4: MIPS (11 Points – 15 minutes)
The MIPS instruction set architecture (ISA) is going to be updated, and the Recording Industry Association of America (RIAA) has asked the designers to add an anti-piracy feature. The new instruction, riaa, will search for copyrighted material in your hard disk. In order to make space for the new instruction, they decided to remove variable logical shifts from the language. Thus, sllv will disappear from MIPS and its (R-type) opcode & function will be used for riaa. Recall the format: sllv $rd, $rt, $rs which shifts the value in register rt to the left by the # of bits specified by register rs and puts the result in destination register rd. We wish to maintain MAL backward-compatibility, so we devise a clever solution in which we consider sllv to be a MAL pseudoinstruction & translate it into a set of TAL instructions that do the same thing. The key idea is that we’re going to use self-modifying code! We’ll stuff the low-order few bits from the contents of the rs register into the shamt field of a vanilla sll instruction (#11 below). We’re telling you how to do it, and your job is to figure out where to put the temporary values (and a few other details). Here are the sll and sllv instructions, and the field widths: 6 5 5 5 5 6 sll 0 rs rt rd shamt 0 sllv 0 rs rt rd 0 4 Thus, the single sllv instruction ($dst, $src and $shamtreg are abstractions for the actual registers) sllv $dst, $src, $shamtreg …would translate to the following set of TAL instructions: (fill in the blanks, we’ve shown comments) 01 add , $0, $shamtreg # copy $shamtreg so we don’t alter it 02 andi , , # The shamt has a maximum size! 03 # shift the shamt to the right location 04 lui $at, shiftLby0(upper) # This lui and the following ori serve to… 05 ori , $at, shiftLby0(lower) # “point” to the shiftLby0 instruction 06 lw , 0( ) # reg now contains the shiftLby0 inst 07 # “paste” shamt into instruction 08 lui $at, shiftLby0(upper) # Again, lui and the following ori serve to… 09 ori , $at, shiftLby0(lower) # “point” to the shiftLby0 instruction 10 sw , 0( ) # Self-modify our code! 11 shiftLby0: sll $dst, $src, 0 # The shiftLby0 instruction
This concludes the Midterm-level questions. You’re 2/
rds
of the way through!
Name: _______________________________ Login: cs61c-____
Question F2: Control and Datapath (18 Points – 24 Minutes)
Modify the following single cycle MIPS datapath diagram to accomodate a new instruction swai (store word then auto-increment). The operation performs the regular sw operation, then post-increments the rs register by 1. Your modification may use simple adders, mux chips, wires, and new control signals. You may replace original labels where necessary. Recall the RTL for sw is: Mem[ R[rs] + SignExt[imm16] ] = R[rt]; PC=PC+4, & that sw (and swai) has the following fields: Opcode Rs Rt Immediate a) Modify the picture above and list your changes below. You may not need all the boxes. Please write them in “pipeline stage order” (i.e., changes affecting IF first, MEM next, etc) (A) (B) (C) (D) (E) (F) b) We also wish to do the same thing with lw, namely create lwai. Will this work? Circle YES or NO and argue your point in one sentence. (3 points) YES NO because
Question F3: Pipelining (18 points, 24 minutes)
Given the following MIPS code snippet (note that instruction #6 could be anything): loop: 1 addi $t0, $t0, 4 2 lw $v0, 0($t0) 3 sw $v0, 20($t0) 4 lw $s0, 60($t0) 5 bne $s0, $0, loop 6 ## The following instruction could be anything! a) Detect hazards and insert no-ops to insure correct operation. Assume no delayed branch, no forwarding units and no interlocked pipeline stages. Your answer on the right should take the form of pair(s) of numbers: num@location – indicating num no-ops should be placed at location. E.g., if you wanted to place 6 noops between lines 2 and 3 (i.e., location=2.5) and 8 noops between lines 5 and 6 (i.e., location=5.5), you would write: “[email protected], [email protected]”. (6 points) Scratch space b) Now, reorder/rewrite the program to maximize performance. Assume delayed branch and forwarding units, but no interlocked pipeline stages. For unknown reasons, the first instruction after the loop label must be the addi. Feel free to insert no-ops where needed. You should be able to do it using 6 instructions per loop (easier, half credit) or only 5 (hard, full credit). (12 pts)
Extra instructions before the loop if necessary
Extra instructions before the loop if necessary
loop: 1 addi $t0, $t0, 4 2 3 4 5 6
The following instruction could be anything!
Question F5: Performance & I/O (18 points, 24 minutes)
a) …and CPIi for each instruction i: What should the CPI of Load/Store for machine A be so that A and B have the same execution performance for this particular instruction mix? Show your work below and put your answer directly in the table above. (5 points) b) We want to send a message between two machines. We’re using Gigabit ethernet & the message (including header & trailer) is 1,000 bytes long. Fill the table; show work! (5 pts) What’s the network transmission time? What (send+receive) overhead causes effective bandwidth to drop to 10Mb/s? We want a single number. c) Answer the following short-answer questions in at most three words (8 pts): Some critics say RAID 0 is a misnomer! What do they say is a more appropriate acronym for RAID 0? (Hint: what is it missing?) In retrospect, the inventors of RAID bemoaned they should have added a RAID 6 level. What would it have gracefully allowed (that RAID 0-5 doesn’t)? Which I/O device we discussed had the highest data rate? Dave Patterson and his ROC team argue that we’ve been focusing on performance almost to excess. What does he believe should be the new benchmarks? Machine ALU Load/Store Branch 20% 30% 50% Machine Clock speed ALU Load/Store Branch A 3 GHz 3 3 B 1 GHz 1 1 2 a) Given the following instruction mix:
