Download CS61C Final Exam at UC Berkeley - Electrical Engineering and Computer Sciences and more Exams Structural Analysis in PDF only on Docsity!
University of California, Berkeley – College of Engineering
Department of Electrical Engineering and Computer Sciences Spring 2007 Instructor: Dan Garcia 2007 - 05 - 12
CS61C Final Exam
After the exam, indicate on the line above where you fall in the emotion spectrum between “sad” & “smiley”... Last Name First Name Student ID Number Login (^) cs61c- Login First Letter (please circle) a^ b^ c^ d^ e^ f^ g^ h^ i^ j Login Second Letter (please circle) a^ b^ c^ d^ e^ f^ g^ h^ i^ j^ k^ l^ m n o p q r s t u v w x y z Your LAB TA’s name (please circle) Aaron Alex Brian David Matt Michael Valerie Name of the person to your Left Name of the person to your Right All the work is my own. I have no prior knowledge of the exam contents nor will I share the contents with others in CS61C who have not taken it yet. (please sign)
Instructions (Read Me!)
- This booklet contains 9 numbered pages including the cover page. Put all answers on these pages (feel free to use the back of any page for scratch work); don’t hand in any stray pieces of paper.
- Please turn off all pagers, cell phones & beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every other seat. Nothing may be placed in the “no fly zone” spare seat/desk between students. The exam is closed book, no computers, PDAs or calculators.
- Fill in the front of this page and put your name & login on every sheet of paper.
- You may use 2 pages (US Letter, front and back) of notes, plus the green COD 3/e reference sheet.
- There may be partial credit for incomplete answers; write as much of the solution as you can. We will deduct points if your solution is far more complicated than necessary. When we provide a blank, please fit your answer within the space provided. “IEC format” refers to the mebi, tebi, etc prefixes.
- You must complete ALL THE QUESTIONS , regardless of your score on the midterm. Clobbering only works from the Final to the Midterm, not vice versa. You have 3 hours...relax.
Problem M1 M2 M3 Ms F1 F2 F3 F4 F5 Fs Total
Minutes 20 20 20 60 24 24 24 24 24 120 180
Points 10 10 10 30 18 18 18 18 18 90 120
Score
Midterm Revisited M1) Do you remember when… we used to sing, sha la la la… a) Some say bubble-gum pop music is garbage, so let’s start with a question about memory management and running programs! BRIEFLY tell us why the first thing is better than the second thing: Mark & sweep is better than reference counting because it... Reference counting is better than copying because it... Copying is better than mark & sweep because it... The buddy scheme is better than the slab allocator because it... The slab allocator is better than the plain K&R free list because it... Compiling is better than interpreting because ... Interpreting is better than compiling because... Dynamic linking is better than Static linking because... Static linking is better than Dynamic linking because... b) Decode the binary numbers into MIPS instructions with proper register names ($s0, $t0, etc.). If there are any memory addresses, represent them in hex. Address 32 - bit Binary Instruction Type (R, I, J) MIPS Instruction w/args 0xAFFFFFF8 0000 0001 0000 1000 0100 0000 0010 0110 0xAFFFFFFC 0001 0100 0000 1000 1111 1111 1111 1110 0xB0000000 0000 1000 0000 0000 0000 0000 0000 0001 0xB0000004 ...whatever... ...whatever... ori $v0, $0, 0x61C 0xB0000008 ...whatever... ...whatever... jr $ra c) You can replace the first instruction with a new instruction and save 2 clock cycles on a single-cycle non-delayed branch MIPS machine. What is it (in MIPS)? Careful! _______________
M3) Because I MIPS you, baby, and I don’t want to C a thing… What follows is a self-modifying MAL MIPS function. Read it carefully, and answer the questions below. A) What is the equivalent C code for mystery? Assume for this part that we only call mystery once. B) When we call mystery the second time with the same arguments we used the first time , do we get the same answer? If not, what do we get? (assume it’s not an error) C) Replace as few nops as possible by the done: label so that mystery behaves as it did in part A every time it’s called, not just the first time. mystery: la $t0, loop addu $v0, $0, $ loop: beq $a1, $0, done lw $t1, 0($a0) addu $v0, $v0, $t lw $t1, 4($t0) addiu $t1, $t1, 4 sw $t1, 4($t0) addiu $a1, $a1, - 1 j loop done: nop nop nop jr $ra // Precondition: 0 < a1 < 215 __________ mystery (___________ a0, int a1) { } done: __________________________
jr $ra
Post-Midterm Questions F1) Code bugs are terrified of RA-AI-AID!!! (Poof!)
- If you put 5 drives with a mean time to failure (MTTF) of 10 years in a RAID 0 array, what will be the MTTF of the array?
- In an interrupt service routine, should the ready bit of a device be checked before accessing it?
- A CPU running some program was found to have a CPI is 2.5 and, on average, 5 ns of CPU time were used per instruction. What is the clock speed in Gigahertz?
- What are the two largest challenges that prevent parallel programs from achieving perfect speedup equal to the number of processors? a) b)
- What does Professor Patterson (and team) want to put into the hands of every systems researcher very soon?
- Rather than endlessly trying to create bug-free programs and somehow find users & operators that never make mistakes (or even trying to eliminate the human element altogether), where does Professor Patterson believe we should focus our efforts?
- What does the receiver do with a packet if its checksum indicates it was corrupted in transit?
F3) On a final exam, a little cache can boost your performance...
No, we can’t be bribed, but we can improve our memory access time...let’s take a look! a) For the purposes of this question, assume our MIPS processor has two levels of data caches with the capabilities shown in the table on the right. Also assume:
- It takes 100 cycles to go to memory
- 1GiB of physical address space Fill in the table on the right. b) In software, you decide to live on the wild side so you turn OFF your L2 cache and clear your L1 cache. Here are other features:
- 4 GiB of virtual address space
- 2 KiB page size
- 8 - entry TLB, LRU replacement
- 32 MiB ARRAY_SIZE
- char A[] starts at a block & page boundary (i.e., block, page aligned)
- The following code is run on the system with no other users and process switching turned off. main() { int i,j; char *A = (char ) malloc (ARRAY_SIZE * sizeof(char)); // block,page aligned for (i = 0 ; i < (ARRAY_SIZE/STRETCH) ; i++) { // # of STRETCHes for (j = 0 ; j < STRETCH ; j++) sum += A[iSTRETCH + j]; // go up to STRETCH for (j = STRETCH- 1 ; j >=0 ; j--) prod = A[iSTRETCH + j]; // down from STRETCH } } i. What is number of bits used for the VPN (assume byte addressing)? ____________________ ii. What is number of bits used for the PPN (assume byte addressing)? ____________________ iii. As we double our STRETCH from 1 to 2 to 4 (...etc), we notice the number of cache misses doesn’t change! What is the largest value of STRETCH before cache misses changes? (Use IEC terms, like 64 TiB, 128 GiB, etc.) ____________________ iv. If we double the STRETCH from (iii), what is ratio of cache hits to misses? ____________________ v. As we double our STRETCH from 1 to 2 to 4 (...etc), we notice the number of TLB misses doesn’t change! What is the largest value of STRETCH before TLB misses changes? (Use IEC terms, like 64 TiB, 128 GiB, etc.) ____________________ vi. For any value of STRETCH what is the fewest number of page faults we could ever generate? (Use IEC terms, like 64 TiFaults, 128 GiFaults, etc.) ____________________
L1 L
Cache Data Size 32 KiB 512 KiB Block Size 8 B 32 B Associativity 4 - way Direct-mapped Hit Time 1 cycle 33 cycles Miss Rate 10% 2% Write Policy Write-through Write-through Replacement Policy LRU LRU Tag Index Offset AMAT (in clock cycles)
F4) Don’t just sit and wait for another datapath you by! On the right is the single-cycle MIPS datapath presented during lecture. Ignore pipelining for the question. Your job is to modify the diagram to accommodate a new MIPS instruction. Your modification may use simple adders, shifters, mux chips, wires, and new control signals. If necessary, you may replace original labels. We want to add a new MIPS instruction (we’ll call it addpr for “add to pointed reg”) that is almost identical to addi but with a twist. Instead of storing into the rt register the sum of the constant and the value of the register specified by rs, it stores into the rt register the sum of the constant and the value of the register specified by the lowest 5 bits in memory at the address specified by the pointer stored in the rt register. Said another way, first get the pointer stored in the rt register. Follow that pointer to get its value from memory. Take the lowest 5 bits of that value, treat is as a register number, and find out what is stored in that register. Add that to the immediate, and store it in the rt register. a) Make up the syntax for the I-type MAL MIPS instruction that does it (show an example if the pointer lives in $v0, and the constant is 5). On the right, show the register transfer language (RTL) description of addpr. Syntax RTL b) Change as little as possible in the datapath above and list all changes below. You may not need all boxes. (i) (ii) (iii) c) We now want to set all the control lines appropriately. List what each signal should be, an intuitive name or {0, 1, x – don’t care}. Include any new control signals you added. RegDst RegWr nPC_sel ExtOp ALUSrc ALUctr MemWr MemtoReg d) In the context of a single-cycle CPU, lw used to be the “critical path” instruction that really determined our fastest clock period, since it utilized the most components of our datapath. Using the terms below to create an expression that will determine how much slower our clock period will be if we also consider the addpr instruction: PCRegClkToQ, InstMemAccess, ControlLogicDelay, RegFileAccess, ALUdelay, DataMemAccess, RegSetup, RegHold, MemSetup, MemHold_._
