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Comparators - Principles of Computer Architecture - Lecture Slides, Slides of Advanced Computer Architecture

Amity University - BiharAdvanced Computer Architecture

In this short course we study the basic concept of the principle of computer architecture. In these lecture slides the key points are:Comparators, Programmable Logic Arrays, Truth Tables, Arbitrary Functions, Arithmetic Circuits, Adders, Ripple Carry Adder, Carry Select Adder, Arithmetic Logic Units, Bit Slices, Clock Cycle Time, Latches

Typology: Slides

2012/2013

Uploaded on 04/23/2013

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Comparators
–A comparator compares two input words.
–The following slide shows a simple comparator
which takes two inputs, A, and B, each of length 4
bits, and produces 1 if they are equal and a 0 if
they are not equal.
•The circuit is based on the XOR gate (EXCLUSIVE OR)
gate, which puts out a 0 if its inputs are equal and a 1 if
they are unequal.
•If the two words are equal, all four of the XOR gates
must output 0. The results are then combined with a
NOR gate.
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Comparators

  • A comparator compares two input words.
  • The following slide shows a simple comparator which takes two inputs, A , and B , each of length 4 bits, and produces 1 if they are equal and a 0 if they are not equal. - The circuit is based on the XOR gate (EXCLUSIVE OR) gate, which puts out a 0 if its inputs are equal and a 1 if they are unequal. - If the two words are equal, all four of the XOR gates must output 0. The results are then combined with a NOR gate.

Comparators

Programmable Logic Arrays

Programmable Logic Arrays

  • The output consists of six OR gates, each of which has up to 50 inputs, corresponding to the 50 outputs of the AND gates. Once again a user supplied (50 x 6) matrix determines which connections actually exist.
  • A PLA can be used to compute the majority function described previously. Examine the diagram for the circuit. By using just 3 of the 12 PLA inputs, four of its 50 AND gates, and one of its six OR gates, we can implement the circuit. Actually, we could wire the PLA to compute simultaneously a total of four functions of similar complexity.

Arithmetic Circuits

  • We now move from general-purpose MSI

circuits to MSI combinatorial circuits used for

doing arithmetic.

  • The first arithmetic MSI circuit we will examine is an eight-input, eight-output shifter.
  • Eight bits of input are presented on lines D 0 , … , D 7. The output, which is just the input shifted 1 bit is available on lines S 0 , … , S 7. The control line, C, determines the direction of the shift, 0 for left and 1 for right.

Adders

Adders

Adders

  • A half adder is adequate for summing the low-

order bits of two multiple input words, it will not do for a bit position in the middle of the word because it does not handle the carry into the position from the right.

  • For this, we need the full adder. A full adder is

built up from two half adders.

  • Together the two half adders generate both the

sum and the carry bits.

Adders

  • To build an adder for, say, two 16-bit words one just replicates the circuit 16 times. The carry out of a bit is used as the carry into its left neighbor. The carry into the rightmost bit is wired to 0.
  • This type of adder is called a ripple carry adder because in the worst case, adding 1 to 111 … 111 (binary), the addition cannot complete until the carry has rippled all the way from the rightmost bit to the leftmost bit. Adders without this delay are preferred.

Adders

  • Consider giving the adder two upper halves operating in parallel by duplicating the upper half’s hardware. Now instead of a single 32-bit adder, we have three 16-bit adders.
  • Call the upper halves U0 and U1. A 0 is fed into U as a carry and a 1 is fed into U1 as a carry. Now both start at the same time as the lower half starts, but only one will be correct. Select the correct one based on the lower half’s output. This is called a carry select adder. And the replication can be repeated.

Arithmetic Logic Units

Arithmetic Logic Units

  • The lower left-hand corner of the ALU contains a 2-bit decoder to generate enable signals for the four operations, based on the control signals F 0 and F 1. Exactly one of the four enable lines is selected.
  • A or B can be forced to 0 by negating ENA or ENB, respectively. It is also possible to get A’, by setting INVA. Under normal conditions, ENA and ENB are both 1 to enable both inputs and INVA is 0. We will later see uses for INVA, ENA, and ENB.

Arithmetic Logic Units

Clocks

  • In many digital circuits the order in which events happen is critical.
  • To allow designers to achieve the required timing relations, many digital circuits use clocks to provide synchronization.
  • A clock is a circuit that emits a series of pulses with a precise pulse width and precise interval between consecutive pulses. - The time interval between the corresponding edges of two consecutive pulses is known as the clock cycle time.