CSE140 Exercise 6
1. Adders: Prove that for two’s complement number system arithmetic, the overflow
of the addition is determined by the last two carry bits, i.e. overf low f lag =
cnLcn−1.
2. Adders: A carry look ahead adder inputs two-bit numbers (a1, a0) and (b1, b0),
and a carry in c0. Use a minimal two-level NAND gate network to implement the
carry out c2.
3. Subtracter: A subtracter inputs a two-bit number (x1, x0), a subtrahend (y1, y0)
and a borrow-in bit b0, and outputs the difference (d1, d0) and a borrow-out bit b2.
3.1. Write the boolean expression of borrow-out bit b2as a function of variables
x1, x0, y1, y0, b0.
3.2. Use two full adders and a minimal number of AND, OR, NOT gates to imple-
ment a look-ahead subtracter. Draw the schematic diagram.
4. Serial Adders: A sequential adder inputs ai, bi, the i’th bit of two binary numbers
in each clock cycle for i= 0 to n−1 and outputs the sum si. Implement the
adder with a JK flip-flop, and a minimal AND-OR-NOT network (if the network is
needed). Draw the schematic diagram.
5. Counters: Given modulo-16 counters, draw the logic diagram to show the fol-
lowing designs.
5.1. Design a module-200 counter with a repeated output.
5.2. Design a counter with a repeated output sequence 15, 0, 1, 2, 8, 9, 10, 6, 7,
with a modulo-16 counter and a minimal combinational network.Write the Boolean
expression and draw the schematic diagram.
6. Design a counter with a repeated output sequence 0, 1, 2, 4, 5, 6, 3, with
a modulo-8 counter and a minimal AND-OR-NOT network. Write the Boolean
expression and draw the schematic diagram.
7. System Designs: Implement the following algorithm.
Alg(X, Y, Z , start, U, done);
Input X[7 : 0], Y [7 : 0], Z [7 : 0], start;
Output U[7 : 0], done;
Local-object A[7 : 0], B[7 : 0], C [7 : 0];
S1: If start0goto S1;
S2: done <= 0 || A <=X|| B <=Y|| C <=Z;
S3: A <=Add(A, B);
S4: If B0[7] goto S3 || B <=I nc(B);
S5: If C0[7] goto S3 || C <=I nc(C);
S6: U <=A|| done <= 1 || goto S1;
End Alg
7.1. Design a data subsystem that is adequate to execute the algorithm. Draw the
schematic diagram to show the design.
7.2. Design the control subsystem (i) draw the state diagram; (ii) draw the logic
diagram that implements the control subsystem with a one hot encoding design.
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