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Overflow
Overflow cases:
Prove that for two's complement number system arithmetic, theoverfow of the addition is determined by the last two carry bits, i.e. overflow flag = c
n
c
n-
Adding two positive numbers
overflow iff s
n-
Adding two negative numbers
overflow iff s
n-
Adding two numbers with different signs
never overflow
a
n-
= b
n-
c
n
always = 0, s
n-
= 1 iff c
n-
overflow iff c
n
c
n-
overflow iff c
n
c
n-
a
n-
= b
n-
c
n
always = 1, s
n-
= 0 iff c
n-
Why?
a
n-
b
n-
c
n
always = c
n-
c
n
c
n-
Carry Look Ahead (CLA) Adder A carry look ahead adder inputs two-bit numbers (a1; a0) and (b1; b0),and a carry in c0. Use a minimal two-level NAND gate network toimplement the carry out c2.
c1 = a0b0 + (a0+b0)c0c2 = a1b1 + (a1+b1)c
= a1b1 + (a1+b1)a0b0 + (a1+b1)(a0+b0)c0= a1b1 + a1a0b0+ b1a0b0 + a1a0c0 + b1a0c0 + a1b0c0 + b1b0c
st
level: one 2-input NAND and six 3-input NAND
nd
level: one 7-input NAND
p1 = a1+b1,g1 = a1b1, p0 = a0+b0, g0 = a0b0,
Simplification: use 3-level logic 1
st
level:
st
and 3
rd
levels: c2 = g1 + p1g0 + p1p0c
Total gates: three 2-input AND, one 3-input AND
two 2-input OR, one 3-input OR
Carry Look Ahead (CLA) Adder
c
1
= g
0
+ p
0
c
0
c
2
= g
1
+ p
1
c
1
= g
1
+ p
1
g
0 +
p
1
p
0
c
0
c
3
= g
2
+ p
2
c
2
= g
2
+ p
2
g
1 +
p
2
p
1
g
0 +
p
2
p
1
p
0
c
0
c
4
= g
3
+ p
3
c
3
= g
3
+ p
3
g
2 +
p
3
p
2
g
1 +
p
3
p
2
p
1
g
0 +
p
3
p
2
p
1
p
0
c
0
g
i
= a
i
b
i
p
i
= a
i
+ b
i
a
3
b
3
g
3
p
3
a
2
b
2
g
2
p
2
a
1
b
1
g
1
p
1
a
0
b
0
g
0
p
0
c
1
c
2
c
3
c
0
CLA block
G
30
P
30
G
3,
P
3,
c
4
6
Step 1: compute
g
i
and
p
i
signals for each single bit in parallel
Step 2: compute
G
and
P
for
-bit blocks
Step 3:
C
0
propagates through each
-bit CLA block
Step 4: compute sum,
s
i
= p
i
c
i
Longest path:
a
0
to
s
15
CLA Adder Delay
G
3,
P
3,
c
16
c
0
G
7,
P
7,
G
11,
P
11,
c
12
c
8
c
4
G
15,
P
15,
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Subtracter A subtracter inputs a two-bit number (x1; x0), a subtrahend (y1; y0)and a borrow-in bit b0, and outputs the dierence (d1; d0) and a borrow-out bit b2. Write the boolean expression of borrow-out bit b2 as afunction of variables x1; x0; y1; y0; b0.
Full subtracter
truth table
x
i
b
i+
y
i
b
i
d
i
d
i
= x
i
y
i
b
i
b
i+
= x
i
’y
i
+ x
i
’b
i
+ y
i
b
i
b1 = x0’y0 + (x0’+y0)b
Therefore we have:
b2 = x1’y1 + (x1’+y1)b
= x1’y1 + (x1’+y1)x0’y0 + (x1’+y1)(x0’+y0)b
Subtracter Use two full adders and a minimal number of AND, OR, NOT gates toimplement a look-ahead subtracter. Draw the schematic diagram. The whole circuit is composed of 3 parts:
Step1: generate g1, g0 and p1, p0 in parallel.
gi = xi’yi
pi = xi’+yi
xi
yi pi
gi
Step2: generate b1 and b2 in parallel.
p
g
p
g
b
b
b
b1 = g0 + p0b0b2 = g1 + p1g0 + p1p0b0 Step3: generate d0 and d1 using full adders. d0 = x
y
b
d1 = x
y
b
x
y
b
d
x
y
b
d
6.5. Counter Counters: Given
modulo-16 counters
, draw the logic
diagram to show the following designs
6.5.1 Design a module-200 counter with a repeated output
Count through 0 to 199(199)
10
2
Q3 Q2 Q
Q
reset
enable
clk
Q7 Q6 Q
Q
reset
enable
clk
Reset the counter after it counts to 199
en
6.5. Counter
6.5.2 Design a counter with a repeated output sequence
with a
modulo-16 counter
and a minimal combinational
network
9-cycle sequence
count from 0 to 8 and then reset
Need to map the counter output to the number sequence
Q3 Q2 Q
Q
reset
enable
clk
Mapping logic O3 O2 O
O
en
15
8
7
7
6
6
10
5
9
4
8
3
2
2
1
1
0
0
O
Q
Mapping logic
6.6 Counter
Design a counter with a repeated output sequence 0, 1, 2,4, 5, 6, 3, with a modulo-8 counter and a minimal AND-OR-NOT network
7-cycle sequence
count from 0 to 6 and then reset
Need to map the counter output to the number sequence
Q2 Q
Q
reset
enable
clk
Mapping logic
O2 O
O
en
3
6
6
5
5
4
4
3
2
2
1
1
0
0
O
Q
Mapping logic
6.7 System Design
Alg(X, Y, Z, start, U, done);
Input X[7 : 0], Y [7 : 0], Z[7 : 0], start;
Output U[7 : 0], done;
Local-object A[7 : 0], B[7 : 0], C[7 : 0];
S1: If start’ goto S1;
S2: done <= 0 || A <= X || B <= Y || C <= Z;
S3: A <= Add(A;B);
S4: If B’[7] goto S3 || B <= Inc(B);
S5: If C’[7] goto S3 || C <= Inc(C);
S6: U <= A || done <= 1 || goto S1;
End Alg
6.7 Operations and Its ControlSignals
A <= XB <=YC <=ZA<=A+BB<=B+1C<=C+1U<=A
operationA
Load (X)
B
Load (Y)
C
Load (Z)
A
Add(A,B)
B
INC(B)
C
INC(C)
Wires
control Ct
0
Ct
1
Ct
2
Ct
3
Ct
4
Ct
5
Hardware components needed:One adder, two counters, a register
6.7 Datapath
A
ld
B
ld
C
ld
adder
MUX
X
Y
Z
s
1
0
Ct
3
Ct
0
Ct
1
Ct
2
inc
Ct
4
inc
Ct
5
6.7 Controller Design
A
ld
B
ld
C
ld
adder
MUX
X
Y
Z
s
1
0
Ct
3
Ct
0
Ct
1
Ct
2
inc
Ct
4
inc
Ct
5
State
State
State
A<=XB<=YC<=Z
A<=A+B
B’[7]
State
B[7]
State
C’[7]
B<=B+
C<=C+
State
C[7]
U<=A
Ct0 = 1Ct1 = 1Ct2 = 1
Ct3 = 1
Ct4 = 1
Ct5 = 1
0 0 0 0 0 0 0
state
0 0 0 0 1 0 Ct
0 0 0 0 0 0
state
0 0 1 0 0 Ct
1
0
0
0
0
state
0
0
0
0
0
state
0
0
0
0
0
state
0
1
0
0
0
state
0
0
1
1
1
state
done
Ct
Ct
Ct
Ct
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