Please Note: To receive full credit, you must use the following best practices in all homework
assignments:
Use meaningful names for modules, ports, and wires when possible.
Use underscores to break up long binary and hex numbers into groups of 4 digits
to make them more readable. Ex: 12’b1001_0011_1101
Show your work if you wish to receive partial credit.
All figures & graphs should include a number and caption (handwritten is OK).
When printing waveforms, ensure that the relevant signal transitions are clearly
visible.
All HDL source must be typed, and at a minimum should be loaded into
ModelSim to ensure syntactic correctness. Syntax errors in HDL source will be
penalized heavily. Do NOT submit handwritten code.
All HDL source developed for any problem must be uploaded to the
corresponding Dropbox on the course website by the homework due date.
1. (4pts) Create a DOC file (using MS Word, Open Office, etc.) containing the following:
Your name (and a hint on pronunciation if necessary)
A photograph of yourself
Your year in school (Junior, Senior, Grad Student, …)
Your department/major
If you have had experience using Verilog or another HDL in another course or job,
briefly mention it.
Save the file as yourname_profile.doc and submit it to the Dropbox on the Learn@UW website.
Additionally, complete the exam time survey on the Learn@UW site if you have not already
done so.
2. (6pts) Welcome to ModelSim
Complete the ModelSim tutorial posted on the Learn@UW site and fill in the following
statement.
I solemnly swear under pain of karmic retribution that I have completed the ModelSim tutorial.
If I had any problems, I discussed them with the TA.
Docsity.com
