1. Create your own two-input Verilog module with names called XOR2, AND2, and OR2 using
two input NOR gate. Design a full adder (FA) module using module instantiation of XOR2,
AND2, and OR2. Design a 4-bit adder using the FA module. Write testbench and verify the
logic.
2. Create your own module MUX_2 using NAND gate to realize 2:1 Multiplexer. Design 4:1
Multiplexer module with name MUX_4 using MUX_2 module. Design 8:1 Multiplexer using
using MUX_2 and MUX_4 module. Write testbench to verify the logic.
3. Write Structural level Verilog for the following circuit and verify it by writing test bench
4. Circuits to compute the next value for a 16-bit program counter. RESET and BRANCH are 1-
bit signals, PC and NEXT_PC are 16-bit signals, and OFFSET is an 8-bit signal in 2’s
complement format (i.e., it can be either positive or negative). Write Datflow level Verilog code
and verify it by writing testbench.
