Lab Assignment #03
Task# 01
Create a new project in ModelSim, add the files containing adder/subtactor module and
Stimulus module to the project
Compile and run the simulation of 8-bit adder/subtractor in ModelSim
Display inputs and outputs of 8-bit adder/subtractor using $monitor. Also show timing
waveforms to Lab Instructor
Task# 02
Write Verilog code in behavioral modeling for 8-bit accumulator
Write Stimulus module to verify your accumulator design. Stimulus module should give
inputs to design module and display corresponding outputs using $monitor.
Compile and run the simulation in ModelSim and display output waveforms as well
Task# 03
Write behavioral verilog module for generalized Clock Divider. Also write its Stimulus
in Verilog. Stimulus will instantiate 3 different instances of Clock Divider
Create a ModelSim project, add Clock divider module and its stimulus to project
Compile and run the simulation of Clock Divider in ModelSim and display/verify
outputs
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