Memory Design
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Computer Achitecture and org - Memory Design , Study notes of Computer Architecture and Organization
Detail Summery about Memory Design, Find the Memory characteristics , The hidden Memory Characteristics , puzzle, Memory Design, Memory Address Map.
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2010/2011
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Memory Design
Recap: Find the Memory characteristics that are hidden
Solved puzzle
Memory Design
Available Memory chip Size M
N, W
: N × W
Required memory size: N
× W
Where N
≥ N and W
≥ W
Required number of M
N, W
chips: p × q,
Where p = N
/ N and q = W
/ W
Memory design – Increasing the word size
- Problem - 1
- Design 128 × 16 - bit RAM using 128 × 4 - bit RAM
Solution: p = 128 / 128 = 1; q = 16 / 4 = 4
- Therefore, p × q = 1 × 4 = 4 memory chips of size 128 × 4 are
required to construct 128 × 16 bit RAM
S.No
Memory
Type
N × W N
1
× W
1
p q p * q
x
y z
Total
RAM
128 × 4 128 × 16
x – number of address lines
y (p = 2
y
z – to select the type of memory
Memory Address Map
Component Hexadecimal address
From To
Address Bus
RAM 1.
RAM 1.
RAM 1.
RAM 1.
007F
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
007F
007F
007F
Substitute 0 in place of x to get ‘From’ address and 1 to get ‘To’ address
Memory Design
6 - 0
Data
r/w
Memory Design – Increasing the number of
words
- Problem - 2
- Design 1024 × 8 - bit RAM using 256 × 8 - bit RAM
- Solution: p = 1024 / 256 = 4; q = 8 / 8 = 1
- Therefore, p × q = 4 × 1 = 4 memory chips of size 256 × 8 are required
to construct 1024 × 8 bit RAM
S.NO
Memory N x W N
1
x W
1
P q p * q
x y z
Total
1
RAM 256 × 8
× 8
2
3
4
Memory Design – Increasing the number of words
256 × 8
RAM
Data
Bus
R / W
Address Bus
CS
256 × 8
RAM
Data
Bus
R / W
Address Bus
CS
256 × 8
RAM
Data
Bus
R / W
Address Bus
CS
Address Bus
A
0
- A
7
2 × 4
decoder
256 × 8
RAM
Data
Bus
R / W
Address Bus
CS
A
9
A
8
Data
Bus
R / W
8
0
1
2
3
Design with gates
256 × 8
RAM
Data
Bus
R / W
Address Bus
CS
256 × 8
RAM
Data
Bus
R / W
Address Bus
CS
256 × 8
RAM
Data
Bus
R / W
Address Bus
CS
Address Bus
A
0
- A
7
256 × 8
RAM
Data
Bus
R / W
Address Bus
CS
Data
Bus
8
A
9
A
8
R / W
Memory Design
Problem - 3
Design 256 × 16 – bit RAM using 128 × 8 – bit RAM chips
S.NO
Memory N x W N
1
x W
1
P q p * q
x y z
Total
1
RAM 128 × 8 256 × 16 2 2 4 7 1 0 8
2
3
4
Memory Address Map
Component Hexadecimal address
From To
Address Bus
RAM 1.
RAM 1.
RAM 2.
RAM 2.
007F
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
007F
00FF
00FF
Memory Design
Problem - 4
Design 256 × 16 – bit RAM using 256 × 8 – bit RAM chips
and 256 × 8 – bit ROM using 128 × 8 – bit ROM chips.
S.NO
Memory N x W N
1
x W
1
P q p * q
x y z
Total
1
RAM
256 ×
256 ×
16
2
Rom
128 ×
256 × 8 2 1 2 7 1 1 9
3
4
Memory Address Map
Component Hexadecimal address
From To
Address Bus
RAM 1.
RAM 1.
ROM 1
ROM 2
007F
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
007F
00FF
00FF
x
x