Sequential Logic Design
Lecture #31
•Agenda
1. von Neumann Stored Program Computer Architecture
•Announcements
1. Friday: Thanksgiving Holiday, No classes.
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von Neumann Computer Architecture: Sequential Logic Design Lecture #31, Slides of Digital Logic Design and Programming
An in-depth exploration of the von neumann stored program computer architecture, focusing on the cpu, register loads, control signals, test signals, instruction execution, and control unit sub-operations. Students will learn about the role of the control unit in fetching, decoding, fetching operands, executing instructions, and storing results.
Typology: Slides
2012/2013
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Sequential Logic Design
Lecture
• Agenda
1. von Neumann Stored Program Computer Architecture
• Announcements
1. Friday: Thanksgiving Holiday, No classes.
von Neumann Computer
• CPU
1) Control Unit
2) Processing Unit
3) Control Signals
4) Test Signals
von Neumann Computer
• Control Signals
- the Bus1 and Bus2 control lines come from the control unit and drive the multiplexers
- the WRITE line is a synchronous load to memory from Memory_Out
- CCR_Load will load the status bits (NZVC), whose values depend on the previous ALU operation
- the ALU_Sel line tells the ALU which function to perform (AND, ADD, …)
• Test Signals
- the Instruction Register (IR) holds the Opcode for the Control Unit to base state decisions on
- the CCR_Result is the NZVC status bits from an ALU operation and influence state decisions
von Neumann Computer
• Instruction Execution
State 0
- put the current Program Counter value on the Memory Address Bus to read the first Opcode
RTL: MAR <= PC
Control: Bus1_Sel = PC
Bus2_Sel = Bus
MAR_Load
State 1
- bring in the contents of memory (the Opcode) and put into the IR
- increment PC to point at either the Operand or next Opcode in memory
RTL: IR <= Memory_Out
PC = PC + 1
Control: Bus2_Sel = Memory_Out
IR_Load
PC_Inc
Control Unit Sub-Operations
- Fetch
– Get next instruction into
IR
– PC: program counter,
always points to next
instruction
– IR: holds the fetched
instruction
Processor Control unit Datapath
ALU
Registers
PC IR
Controller
I/O
Control /Status
100 load X, 101 123 102 ADD X, Y
MAR
Y
(^100) load X,
Store X,
X
Control Unit Sub-Operations
- Decode
– Determine what the
instruction means
Processor Control unit Datapath
ALU
Registers
PC IR
Controller
Memory
I/O
Control /Status
100 load X, 101 123 102 ADD X,Y
(^100) load X, MAR X
Y
Control Unit Sub-Operations
- Execute
– Move data through the
ALU
– This particular
instruction does nothing
during this sub-
operation
Processor Control unit Datapath
ALU
Registers
PC IR
Controller
Memory
I/O
Control /Status
100 load X, 101 123 102 ADD X,Y
(^100) load X, MAR X
Y
Control Unit Sub-Operations
- Store results
– Write data from register
to memory
– This particular
instruction does nothing
during this sub-
operation
Processor Control unit Datapath
ALU
Registers
PC IR
Controller
Memory
I/O
Control /Status
100 load X, 101 123 102 ADD X,Y
(^100) load X, MAR X
Y
Instruction Cycles
Processor Control unit Datapath
ALU
Registers
PC IR
Controller
Memory
I/O
Control /Status
100 load X, 101 123 102 ADD X,Y
MAR X
Y
PC= 100
PC= 101
Instruction Cycles
Processor Control unit Datapath
ALU
Registers
PC IR
Controller
Memory
I/O
Control /Status
100 load X, 101 123 102 ADD X,Y