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The Von Neumann

The Von Neumann

Architecture

Architecture

Von Neumann

Von Neumann

Architecture

Architecture

Designing Computers

Designing Computers

All computers more or less based on the same

All computers more or less based on the same

basic design, the

basic design, the

Von Neumann Architecture

Von Neumann Architecture

The Von Neumann

The Von Neumann

Architecture

Architecture

Memory

Processor (CPU)

Input-Output

Control Unit

ALU

Store data and program

Store data and program

Execute program

Execute program

Do arithmetic/logic operations

Do arithmetic/logic operations

requested by program

requested by program

Communicate with

Communicate with

"outside world", e.g.

"outside world", e.g.

Screen

Screen

Keyboard

Keyboard

Storage devices

Storage devices

Bus

Memory Subsystem

Memory Subsystem

Memory, also called

Memory, also called

RAM

RAM

R

R

andom

andom

A

A

ccess

ccess

M

M

emory),

emory),

Consists of many memory cells (storage units) of a fixed size.

Consists of many memory cells (storage units) of a fixed size.

Each cell has an address associated with it: 0, 1, …

Each cell has an address associated with it: 0, 1, …

All accesses to memory are to a specified address.

All accesses to memory are to a specified address.

A cell is the minimum unit of access (fetch/store a complete cell).

A cell is the minimum unit of access (fetch/store a complete cell).

The time it takes to fetch/store a cell is the same for all cells.

The time it takes to fetch/store a cell is the same for all cells.

When the computer is running, both

When the computer is running, both

Program

Program

Data (variables)

Data (variables)

are stored in the memory.

are stored in the memory.

RAM

RAM

Need to distinguish between

Need to distinguish between

the

the

address

address

of a memory cell and

of a memory cell and

the

the content

content of a memory cell

of a memory cell

Memory width (

Memory width (

W

W

How many bits is each memory

How many bits is each memory

cell, typically one

cell, typically one byte

byte (=8 bits)

(=8 bits)

Address width (

Address width (

N

N

How many bits used to represent

How many bits used to represent

each address, determines the

each address, determines the

maximum memory size =

maximum memory size = address

address

space

space

If address width is

If address width is N

N

-bits, then

-bits, then

address space is

address space is 2

NN

NN

...

0

0

1

1

22

2

2

NN

1 bit

1 bit

W

W

0000000000000001

0000000000000001

N

N

N

N

Operations on Memory

Operations on Memory

Fetch (address):

Fetch (address):

Fetch a copy of the content of memory cell with the specified

Fetch a copy of the content of memory cell with the specified

address.

address.

Non-destructive, copies value in memory cell.

Non-destructive, copies value in memory cell.

Store (address, value):

Store (address, value):

Store the specified value into the memory cell specified by address.

Store the specified value into the memory cell specified by address.

Destructive, overwrites the previous value of the memory cell.

Destructive, overwrites the previous value of the memory cell.

The memory system is interfaced via:

The memory system is interfaced via:

Memory Address Register (MAR)

Memory Address Register (MAR)

Memory Data Register (MDR)

Memory Data Register (MDR)

Fetch/Store signal

Fetch/Store signal

Structure of the Memory

Structure of the Memory

Subsystem

Subsystem

Fetch(address)

Fetch(address)

Load address into MAR.

Load address into MAR.

Decode the address in MAR.

Decode the address in MAR.

Copy the content of memory cell with

Copy the content of memory cell with

specified address into MDR.

specified address into MDR.

Store(address, value)

Store(address, value)

Load the address into MAR.

Load the address into MAR.

Load the value into MDR.

Load the value into MDR.

Decode the address in MAR

Decode the address in MAR

Copy the content of MDR into memory

Copy the content of MDR into memory

cell with the specified address.

cell with the specified address.

MAR MDR

...

Memory

decoder

circuit

Fetch/Store

controller

F/S

I/O Controllers

I/O Controllers

Speed of I/O devices is slow compared to RAM

Speed of I/O devices is slow compared to RAM

RAM ~ 50 nsec.

RAM ~ 50 nsec.

Hard-Drive ~ 10msec. = (10,000,000 nsec)

Hard-Drive ~ 10msec. = (10,000,000 nsec)

Solution:

Solution:

I/O Controller, a special purpose processor:

I/O Controller, a special purpose processor:

Has a small memory buffer, and a control logic to control I/O

Has a small memory buffer, and a control logic to control I/O

device (e.g. move disk arm).

device (e.g. move disk arm).

Sends an interrupt signal to CPU when done read/write.

Sends an interrupt signal to CPU when done read/write.

Data transferred between RAM and memory buffer.

Data transferred between RAM and memory buffer.

Processor free to do something else while I/O controller

Processor free to do something else while I/O controller

reads/writes data from/to device into I/O buffer.

reads/writes data from/to device into I/O buffer.

I/O controller

Structure of the I/O

Structure of the I/O

Subsystem

Subsystem

I/O Buffer

Control/Logic

I/O device

Data from/to memory

Interrupt signal (to processor)

Structure of the ALU

Structure of the ALU

Registers:

Registers:

Very fast local memory cells, that

Very fast local memory cells, that

store operands of operations and

store operands of operations and

intermediate results.

intermediate results.

CCR

CCR

(condition code register), a

(condition code register), a

special purpose register that stores

special purpose register that stores

the result of <, = , > operations

the result of <, = , > operations

ALU circuitry:

ALU circuitry:

Contains an array of circuits to do

Contains an array of circuits to do

mathematical/logic operations.

mathematical/logic operations.

Bus:

Bus:

Data path interconnecting the

Data path interconnecting the

registers to the ALU circuitry.

registers to the ALU circuitry.

ALU circuitry

GT EQ LT

R

R

R

Rn

The Control Unit

The Control Unit

Program is stored in memory

Program is stored in memory

as machine language instructions, in binary

as machine language instructions, in binary

The task of the

The task of the

control unit

control unit

is to execute programs

is to execute programs

by repeatedly:

by repeatedly:

Fetch

Fetch

from memory the next instruction to be executed.

from memory the next instruction to be executed.

Decode

Decode

it, that is, determine what is to be done.

it, that is, determine what is to be done.

Execute

Execute

it by issuing the appropriate signals to the

it by issuing the appropriate signals to the

ALU, memory, and I/O subsystems.

ALU, memory, and I/O subsystems.

Continues until the HALT instruction

Continues until the HALT instruction

Instruction Set Design

Instruction Set Design

Two different approaches:

Two different approaches:

Reduced Instruction Set Computers (RISC)

Reduced Instruction Set Computers (RISC)

Instruction set as small and simple as possible.

Instruction set as small and simple as possible.

Minimizes amount of circuitry --> faster computers

Minimizes amount of circuitry --> faster computers

Complex Instruction Set Computers (CISC)

Complex Instruction Set Computers (CISC)

More instructions, many very complex

More instructions, many very complex

Each instruction can do more work, but require more

Each instruction can do more work, but require more

circuitry.

circuitry.

Typical Machine

Typical Machine

Instructions

Instructions

Notation:

Notation:

We use X, Y, Z to denote RAM cells

We use X, Y, Z to denote RAM cells

Assume only one register R (for simplicity)

Assume only one register R (for simplicity)

Use English-like descriptions (should be binary)

Use English-like descriptions (should be binary)

Data Transfer Instructions

Data Transfer Instructions

LOAD

LOAD

X

X

Load content of memory location X to R

Load content of memory location X to R

STORE X

STORE X Load content of R to memory location X

Load content of R to memory location X

MOVE

MOVE X, Y

X, Y Copy content of memory location X to loc.

Copy content of memory location X to loc.

Y

Y

(not absolutely necessary)

(not absolutely necessary)