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BASIC GATES
module basicgate(a, b, c); input a; input b; output [6:0] c; //[6:0]c/ c,d,e,f,g,h,i and(c[0],a,b); or(c[1],a,b); not(c[2],a); nand(c[3],a,b); nor(c[4],a,b); xor(c[5],a,b); xnor(c[6],a,b); endmodule
TEST BENCH module basicgate_tb; reg a; reg b; wire [6:0] c; basicgate uut ( .a(a), .b(b),.c(c) ); –here mention about module name as same as given above initial begin #10 a=1’b0;b=1’b0; –input a=0,b= #10 a=1’b0;b=1’b1; –input a=0,b= #10 a=1’b1;b=1’b0; –input a=0,b= #10 a=1’b1;b=1’b1; –input a=0,b= #10$stop; end endmodule
ENCODER 8*
module encodere(d, a, b, c); input [0:7] d; output a; output b; output c; or(a,d[4],d[5],d[6],d[7]); or(b,d[3],d[2],d[6],d[7]); or(c,d[1],d[3],d[5],d[7]); endmodule
TESTBENCH module encodere_tb; reg [0:7] d; wire a; wire b; wire c; encodere uut (.d(d), .a(a), .b(b),.c(c) ); initial begin #10 d=8'b10000000; #10 d=8'b01000000; #10 d=8'b00100000; #10 d=8'b00010000; #10 d=8'b00001000; #10 d=8'b00000100; #10 d=8'b00000010; #10 d=8'b00000001; end
#10 e=1'b0;a=1'b1;b=1'b1; #10 e=1'b1;a=1'b0;b=1'b0; #10 e=1'b1;a=1'b0;b=1'b1; #10 e=1'b1;a=1'b1;b=1'b0; #10 e=1'b1;a=1'b1;b=1'b1; end endmodule
4 BIT MUX
module mux4bit(a, s, o); input [3:0] a; input [1:0] s; output o; reg o; always @(a or s) begin case (s) 2'b00:o=a[0]; 2'b01:o=a[1]; 2'b10:o=a[2]; 2'b11:o=a[3]; default:o=0; endcase end endmodule
TESTBENCH module muxt_b; reg [3:0] a; reg [1:0] s; wire o; mux4bit uut (.a(a), .s(s),.o(o)); initial begin #10 a=4'b1010; #10 s=2'b00; #10 s=2'b01;
FULL ADDER
module fa(a, b, c, sum, carry); input a; input b; input c; output sum; output carry; wire d,e,f; xor(sum,a,b,c); and(d,a,b); and(e,b,c); and(f,a,c); or(carry,d,e,f); endmodule TEST BENCH module fulladdt_b; reg a; reg b; reg c; wire sum; wire carry; fa uut ( .a(a), .b(b),.c(c),.sum(sum),.carry(carry) ); initial begin #10 a=1’b0;b=1’b0;c=1’b0; #10 a=1’b0;b=1’b0;c=1’b1; #10 a=1’b0;b=1’b1;c=1’b0; #10 a=1’b0;b=1’b1;c=1’b1; #10 a=1’b1;b=1’b0;c=1’b0;
#10 a=1’b1;b=1’b0;c=1’b1; #10 a=1’b1;b=1’b1;c=1’b0; #10 a=1’b1;b=1’b1;c=1’b1; end endmodule
ALU
module alu(s, A, B, F); input [2:0] s; input [3:0] A, B; output [3:0] F; reg [3:0] F; always @(s or A or B) case (s) 0: F = 4'b0000; 1: F = B-A; 2: F = A-B; 3: F = A + B; 4: F = A ^ B; 5: F = A | B; 6: F = A & B; 7: F = 4'b1111; endcase endmodule
