Download ECE 366 Midterm Exam Solutions - Datapath Control & VHDL Code Mod (Fall 2001) and more Exams Computer Architecture and Organization in PDF only on Docsity!
ECE 366, Fall 2001 , Instructor: Prof. Shantanu Dutt
Midterm Exam Solutions
- Datapath Control A datapath is given below.
B
16
16-bit add/sub
X Y I1 I0 sela
lda ldb reset_cntt cnt_up
ldaldb
A
xor Controller (C.U.)
ovfldetect oper
(^16 ) c15 16
cout
ovfl Description of status signals:
cin sela
cnt_up = 1 means Cntr <- Cntr +1 (^) ofvl detect: c15 xor cout reset_cntr = 1 means Cntr <- 0
lda = 1 means load/write A ldb = 1 means load/write B sela = 0 means X is connected to input of reg. A
oper = 0/1 means ADD/SUB resp.
sela = 1 means add/sub output is connected to input of reg. A
ldr = 1 means load/write R ldq = 1 means load/write Q NOTE: All write/cnt up operations complete only at the +ve edge of the next cc (since they all load new values into regs) NOTE: Signal lines without any specified width are 1-bit wide
Description of control signals:
Cntr
ovfl is the overflow indicator s15 is the msb or sign bit of add/sub output
2:1 mux
s
ldr (^) R Q ldq
ldrldqs15ovfl
Description of cominational logic units:
16
16
16
16
xor: xor’s each bit of M w/ "oper" => xor o/p is M if oper=1 else it is M
16
16
(a) Give the Moore state diagram of the FSM for the control unit that performs the following function described below using regular programming language statements: begin cntr=0; A=X; B=Y; while (A B) do begin A = A - B; cntr=cntr+1; endwhile R =A; Q=cntr; end
IMPORTANT: State beside each state of your FSM the RTL description of what is being accom- plished in that state. You will be graded most importantly on correctness of your FSM and then on the speed and number of states of your design. 50 (b) What function of X and Y is stored at the end in R and Q? 10
Solution: (a)
xor Controller (C.U.)
ovfldetect oper
(^16 ) c15 16 cout
ovfl cin ldqs15ovfl
Reset Reset
(s15 xor ovfl)= (s15 xor ovfl)=
cnt_up= lda=1, sela=1,oper=
oper= lda=1, sela=1,
[A <- A-B]
lda=1, sela=1,
oper=0 (^) [A <- A+B] (s15 xor ovfl)= (s15 xor ovfl)= (b) FSM for iter-sub division Analysis: 2Q+3 cc’s (Q is quotient) (c) Faster FSM for iter-sub division (a) Datapath for iterative-subtraction based division Analysis: Q+4 cc’s
ldr
A B
16
16-bit add/sub
X Y I1 I0 sela
lda ldb reset_cntt cnt_up
ldaldbsela
Cntr
2:1 mux
s
ldr (^) R Q ldq
lda=1, ldb=1reset_cntr=
ldr=1,ldq=
(s15 xor ovfl)= (s15 xor ovfl)=
[A-B perf.]
[A <- A-B, Cntr <- Cntr+1] (^) {R <- A. Q <- Cntr]
cnt_up=
oper=
lda=1, sela=1,oper= [A <- A-B,
sela=0, 16
16
16
16
16
16
[A <- X,B <- Y, Cntr <- 0]
sela=0, lda=1, ldb=1reset_cntr= [A <- X,B <- Y, Cntr <- 0]
Cntr <- Cntr+
ldq = 1 means load/write Q
(for prev. sub.)]
ldr=1,ldq= {R <- A.Q <- Cntr]
ovfl is the overflow indicator^ Description of status signals: s15 is the msb or sign bit ofadd/sub output
Description of control signals: cnt_up = 1 means Cntr <- Cntr + lda = 1 means load/write Aldb = 1 means load/write Bsela = 0 means X is connected to reset_cntr = 1 means Cntr <- 0 input of reg. A
oper = 0/1 means ADD/SUB resp.
sela = 1 means add/sub output isconnected to input of reg. A
ldr = 1 means load/write R
(b) Finally R has the remainder and Q the integer quotient of the division X/Y.
Solution: Multiple solutions are possible. Two are given below:
(i) Process code is changed to:
transition: process is
wait until (clk’event and clk=’1’) or (reset=’1’) if reset =’1’ then q = ’0’ after 8 ns; else q = d after 8 ns; if reset =’1’ then wait on reset; else wait on d, reset; end process transition;
(ii) Simpler solution (less effective as process will loop back even when “reset” remains ’1’). Process code is changed to:
transition: process is
wait until (clk’event and clk=’1’) or (reset=’1’) if reset =’1’ then q = ’0’ after 8 ns; else q = d after 8 ns; wait on d, reset; end process transition;
- Timing Diagram^5 Condider the following VHDL code in which two processes communicate using signalling (hand- shaking). entity comm modules is end entity comm modules; architecture behav of comm modules is signal read, dataready : bit := ’0’; signal data: integer; begin consumer: process is variable reg1, reg2: integer; begin wait until dataready =’0’;
read = 1 after 20 ns; – signalling for next data item
- 20 ns is the delay of the “read” signal to reach the “producer”
- process, i.e., 20 ns is the “read” signal’s propagation delay.
- Note that the above signal assignment statement with a delay of 20 ns
- does NOT advance simulation time; it only causes the “read” signal
– to become ‘1’ at time ns where is the current simulation time.
- Since there is no advance of simulation time, the next statement below
- is executed without any further time elapsing since the execution of the
– above signal assignment statment. i.e., it is executed at time .
wait until dataready =’1’;
- note that “wait” statement (of all types) causes an advance of simulation time.
– Thus in the above statement, if is the current simulation time
– and if “dataready” becomes ’1’ after ns ( ) from the
– current time, then the next statement is executed at time ns.
reg1 := data; – store sent data in register reg
read = 0 after 20 ns;
wait for 10 ns; – simulating time to process data in reg reg2 := reg1; – simulating storing processed data in reg
- can now loop back to obtain next data item end process consumer;
Solution :
15 20 25 30 35 40 45 50 55 60 65
0
1
0 dataready
read
data (^) invalid
(a) Timing Chart
0 ns 70 ns
valid data for iteration 1
t= 5 10
