Control Unit of Processor - Computer Organization - Homework, Exercises of Computer Architecture and Organization

These HOMEWOR NOTES are very easy to understand and very helpful to built a concept about the foundation of computers ORGANIZATION and Database Design.The key points in these slide are:Computer Processors, Instruction Set Architecture, Assembly Language Statement, Addressing Mode, Register Values After Execution, Unmodified Register, Memory Values, Insertion Sort Algorithm, Assembly Language Code Computer Processors, Instruction Set Architecture, Assembly Language Statement, Addressing Mode, Reg

Typology: Exercises

2012/2013

Uploaded on 04/27/2013

arundhati
arundhati ๐Ÿ‡ฎ๐Ÿ‡ณ

4.5

(23)

88 documents

1 / 3

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
1. Recall that the control unit of the processor drives the Fetch-Execute instruction cycle by generating an
appropriate sequence of control signals. Consider the following simple computer.
The fetch of the next instruction pointed at
by the PC needs the following steps
(micro-operations):
[MAR] โ† [PC]
[PC] โ† [PC] + 1 (Increment PC)
[MBR] โ† Memory read from MAR addr.
[IR] โ† [MBR]
Once fetched into the IR, the LOAD R0, M
instruction needs the following steps to
execute:
[MAR] โ† [IR]
Address
[MBR] โ† Memory read from MAR addr.
[R0] โ† [MBR]
a) What would be the steps needed to
execute the STORE M, R1 instruction?
b) What would be the steps needed to
execute the ADD R1, R0 instruction?
c) What would be the steps needed to
execute the BRA T instruction?
d) What would be the steps needed to
execute the BEQ T instruction?
Computer Org. Lecture 20 Name:_______________
Lecture 20 Page 1
Docsity.com
pf3

Partial preview of the text

Download Control Unit of Processor - Computer Organization - Homework and more Exercises Computer Architecture and Organization in PDF only on Docsity!

  1. Recall that the control unit of the processor drives the Fetch-Execute instruction cycle by generating an appropriate sequence of control signals. Consider the following simple computer.

The fetch of the next instruction pointed at by the PC needs the following steps (micro-operations): [MAR] โ† [PC] [PC] โ† [PC] + 1 (Increment PC) [MBR] โ† Memory read from MAR addr. [IR] โ† [MBR] Once fetched into the IR, the LOAD R0, M instruction needs the following steps to execute: [MAR] โ† [IR]Address [MBR] โ† Memory read from MAR addr. [R0] โ† [MBR] a) What would be the steps needed to execute the STORE M, R1 instruction?

b) What would be the steps needed to execute the ADD R1, R0 instruction?

c) What would be the steps needed to execute the BRA T instruction?

d) What would be the steps needed to execute the BEQ T instruction?

Computer Org. Lecture 20 Name:_______________

Lecture 20 Page 1Docsity.com

  1. Add โ€œhardwareโ€ (gates, MUX, decoder, etc.) to Figure 7.1 to allow for:a) BEQ T which has the micro-operation: IF [Z] = 1 THEN [PC]

T

b) The MBR needs to be able receive data from two places: Memory and Bus A. Add hardware to allow this with a control signal MBR C

MUX

  1. (a) Complete the control signals for its micro-operations needed for the fetch-execute of the LOAD R0, M instruction:

T^6 T^7

R โ† MBR

T^5

MBR

โ†

M[MAR]

T^4

MAR

โ†

IR

Address

Execute

T^3

IR^ โ†^

MBR

T^2

MBR

โ†

M[MAR]

T^1

PC โ†

PC + 1

T^0

MAR

โ† PC

Fetch

MBRCMUX F^0 F^1 F^2 ER1_C ER0_C EMBR_C ER1_B ER0_B EIR_B EPC_B EMBR_B CR CR CIR CPC CMBR CMAR MemWrite MemRead Step#

RTN

Step b) Complete the control signals for its micro-operations needed for the fetch-execute of the STORE M, R1 instruction:

T^6 T^7

M[MAR]

โ†

MBR

T^5

MAR

โ† IRAddress

T^4

MBR

โ†

R

Execute

T^3

IR^ โ†^

MBR

T^2

MBR

โ†

M[MAR]

T^1

PC โ†

PC + 1

T^0

MAR

โ† PC

Fetch

MBRCMUX F^0 F^1 F^2 ER1_C ER0_C EMBR_C ER1_B ER0_B EIR_B EPC_B EMBR_B CR CR CIR CPC CMBR CMAR MemWrite MemRead Step#

RTN

Computer Org. Step

Lecture 20

Name:_______________

Lecture 20 Page 2

Docsity.com