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These HOMEWOR NOTES are very easy to understand and very helpful to built a concept about the foundation of computers ORGANIZATION and Database Design.The key points in these slide are:Computer Processors, Instruction Set Architecture, Assembly Language Statement, Addressing Mode, Register Values After Execution, Unmodified Register, Memory Values, Insertion Sort Algorithm, Assembly Language Code Computer Processors, Instruction Set Architecture, Assembly Language Statement, Addressing Mode, Reg
Typology: Exercises
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The fetch of the next instruction pointed at by the PC needs the following steps (micro-operations): [MAR] โ [PC] [PC] โ [PC] + 1 (Increment PC) [MBR] โ Memory read from MAR addr. [IR] โ [MBR] Once fetched into the IR, the LOAD R0, M instruction needs the following steps to execute: [MAR] โ [IR]Address [MBR] โ Memory read from MAR addr. [R0] โ [MBR] a) What would be the steps needed to execute the STORE M, R1 instruction?
b) What would be the steps needed to execute the ADD R1, R0 instruction?
c) What would be the steps needed to execute the BRA T instruction?
d) What would be the steps needed to execute the BEQ T instruction?
b) The MBR needs to be able receive data from two places: Memory and Bus A. Add hardware to allow this with a control signal MBR C
MUX
R โ MBR
MBR
โ
M[MAR]
MAR
โ
Address
Execute
IR^ โ^
MBR
MBR
โ
M[MAR]
PC โ
PC + 1
MAR
โ PC
Fetch
MBRCMUX F^0 F^1 F^2 ER1_C ER0_C EMBR_C ER1_B ER0_B EIR_B EPC_B EMBR_B CR CR CIR CPC CMBR CMAR MemWrite MemRead Step#
Step b) Complete the control signals for its micro-operations needed for the fetch-execute of the STORE M, R1 instruction:
M[MAR]
โ
MBR
MAR
โ IRAddress
MBR
โ
Execute
IR^ โ^
MBR
MBR
โ
M[MAR]
PC โ
PC + 1
MAR
โ PC
Fetch
MBRCMUX F^0 F^1 F^2 ER1_C ER0_C EMBR_C ER1_B ER0_B EIR_B EPC_B EMBR_B CR CR CIR CPC CMBR CMAR MemWrite MemRead Step#
Lecture 20 Page 2