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Spring 2008 Nios II Assembly Language Basics
NIOS II Processor System Architecture and Programming
Developing assembly language programs requires understanding the architecture of the system before one can start producing code. So, we will begin with a simplified view of the Nios II system.
Figure 1. Simplified Nios II Microprocessor System
Above is a simplified depiction of the Nios II microprocessor system. It contains a processor and attached external memory. The processor contains a control unit and general purpose registers. Within the control unit is a 32-bit value called the program counter (PC) that acts as a pointer into program memory.
Memory can be viewed as an array of consecutive units that can be addressed individually or in groups. Each unit is a byte (8 bits) and has a unique address. The Nios II processor uses 32-bit addresses and therefore can address up to 2^32 =4,294,967, bytes. Thus the address space is referenced at the byte level. This means that each address refers to a unique byte.
The processor can only change data that resides in registers. For this reason the standard sequence of all assembly language programs is to first move data from memory to registers, perform operations on the data in registers and then move the resulting data in registers back to memory. Also using instructions that alter the sequence of operation will result in programs that cover the majority of all applications.
For the purposes of this example we will consider four basic groups of instructions. These are instructions that move data from memory to registers (MR), move data from registers to memory (RM), operate on register values placing results back into a register (RR) and finally change the flow (FC) of the instruction sequence. When instructions from the first three groups (MR, RR, RM) are executed, the program counter (PC) is
0x 0x
0x00B
0x7FF 0x
0x00C 0x00D
Processor Memory Address Space
Registers
Control Unit (^) Instr 1 Instr 2 Instr 3 …
Data 1 Data 2 Data 3 …
Program Memory
Data Memory
PC = 0
r0 r1 r2 r r4 r5 r6 r r8 r9 r10 r r12 r13 r14 r r16 r17 r18 r r20 r21 r22 r r24 r25 r26 r r28 r29 r30 r
Spring 2008 Nios II Assembly Language Basics
incremented by 4 (next sequential instruction). The last group of instructions allows the sequence of instructions to be changed.
There are several key elements needed to understand the system environment and the selection and placement of instructions and data in a program. The following sections provide an introduction to these elements, including registers and memory and how they interact, plus instructions and directives.
Registers
As shown in Figure 1, the Nios II processor has thirty-two 32-bit general purpose registers. Some of these registers are intended for a specific purpose as shown in Table 1, and have special names that are recognized by the Assembler. The purpose of these reserved registers will be covered in a later lab. Registers r2 through r23 are available for general use.
Register Name Function r r r r . . . r r r r r r r r r
zero at
et bt gp sp fp ea ba ra
0x Assembler Temporary
Exception Temporary Breakpoint Temporary Global Pointer Stack Pointer Frame Pointer Exception Return Address Breakpoint Return Address Return Address Table 1. Special and general purpose registers in Nios II.
Program Counter
Note PC=0 in the control unit shown in Figure 1. This indicates the program counter (PC) in Figure 1 is pointing to address 0 in program memory. With PC=0 the next instruction to be executed will be “Instr 1”.
When a processor is reset the PC is set to the default value of the processor (usually zero). So this implies that the first instruction that is to be executed must be at this address. For now we will not worry about how to get the instructions loaded into memory, but will assume that they have been loaded into memory at the appropriate locations.
Spring 2008 Nios II Assembly Language Basics
Data Memory
Figure 3. Memory Organization
Figure 2 shows a typical memory arrangement where each row contains 16 bytes or 4 words of data. As previously noted, the address space is referenced at the byte level. Objects other than bytes may be accessed, but the address must still be a byte address. To access a word (32 bits), the byte address must be on a word boundary (divisible by 4), and to access a half word (16 bits), the address must be on a halfword boundary (divisible by 2).
One feature of RISC processors is that the instruction lengths are constant and are usually 32 bits or 1 word in length. Additionally all assembler instructions must start on a word boundary (divisible by 4) and the PC value will also be a multiple of 4. In Figure 3, instruction 1 is at address 0, instruction 2 is at address 4 and so on. Instructions can read and write words , half words , or bytes (8 bits) of data. Reading or writing to an address that does not correspond to an existing memory or I/O location produces an undefined result.
Since the assembler will generally locate the data for a program immediately after the last program instruction, the first data element will start on a word boundary.
Just as the PC register serves as a pointer into program memory any of the general purpose registers can serve as pointers into data memory. So, in this way the registers can contain data or pointers (addresses) to data. It is the responsibility of the programmer to make sure that the register contains the appropriate data for the application.
The instructions that make up the NIOS II processor can be categorized by type of addressing they utilize. There are five addressing modes provided:
0x 0x
0x00B
0x7FF 0x
0x00C 0x00D
Memory Address Space Instr 1 Instr 2 Instr 3 …
Data 1 Data 2 Data 3 …
Program Memory
Data Memory
Spring 2008 Nios II Assembly Language Basics
- Immediate mode – a 16-bit operand is explicitly given in the instruction. This value may be sign extended to produce a 32-bit operand in instructions that perform arithmetic operations. (RR group) example: addi r2, r4, 16 The immediate value 16 is stored as a part of the addi machine instruction. When executed the 16 bit value is sign extended and added to the value contained in register 4 and the result is place in register 2.
- Register mode – the operand is in a processor register (RR group) example: add r2, r4, r The contents of registers 4 and 5 are added an the contents for register 2 is replaced with the result.
- Displacement mode – the effective address of the operand is the sum of the contents of a register and a signed 16-bit displacement value given in the instruction. (MR and RM groups) example: ldbu r2, 64(r4) The address of the byte to be loaded into register 2 is produced by sign extending the offset of 64 (16 bit immediate) and adding to the contents of register 4. The content of register 4 remains unchanged.
- Register indirect mode – the effective address of the operand is the contents of a register specified in the instruction. This is equivalent to the displacement mode where the displacement value is equal to 0. (MR and RM groups) example: ldw r2, 0(r4) Register 4 contains the address of the word to be loaded into register 2.
- Absolute mode – a 16-bit absolute address of an operand can be specified by using the displacement mode with register r0 (which always contains the value 0). (MR and RM groups) example: ldw r2, 0x20(r0) The word located at memory location 0x20 (32 decimal) is loaded into register 2. Memory locations beyond 0x7fff cannot be accessed via this mode.
Now let’s look at the instructions in a little more detail. The MR, RR and RM instructions all increment the PC by 4 when executed.
Spring 2008 Nios II Assembly Language Basics
All Assembler directives begin with a period. Refer to the GNU manual above to learn about directives, including the common directives listed below:
.text this directive tells the assembler to place the following statements at the end of the code section.
.end Marks the end of current assembly program.
.data this directive tells the assembler to place the following statements at the end of the data section.
.global this directive makes the symbol visible to the program loading instructions into memory.
.equ this directive set the value of a symbol.
.word this directive is used to set the content of memory locations to the specified value.
Additional concepts such as symbols and labels should be understood.
The Special Dot Symbol.
The special dot symbol contains the address the assembler is currently assembling into. Following are some examples of its usage. Also referred to as current location counter.
start: .word. # the current assemble address is stored in memory location .work .-start # difference between address of start and current location counter
name: .ascii “this is a string” name_length: .word .-name
Following pages will show a couple of examples for instruction decoding and encoding.
ECE 332 Nios II Assembly Language Spring 2008 Microprocessors Instruction Decoding
Q. Assume that the following word is a Nios II machine instruction. Decode the instruction and show its assembly language equivalent.
0x1905883a Hexadecimal representation
A. To begin, re-write the instruction in its binary form.
1 9 0 5 8 8 3 A hex value 0001 1001 0000 0101 1000 1000 0011 1010 binary equivalent
Then re-group rightmost 6 bits to identify the opcode.
0001 1001 0000 0101 1000 1000 00 111010 regroup for opcode
0x3A hex opcode
So, the opcode is a hex 0x3A. Now utilizing the opcode table from Instruction Set Reference manual we can find the instruction’s mnemonic.
This tells us that the instruction is an R-type instruction and requires further work to identify the instruction’s identity. R-type instructions have the following format with the OPX field to identify the operation.
R-type
Further re-grouping to isolate the OPX bits shows that a hex 0x31 occupies these bits.
ECE 332 Nios II Assembly Language Spring 2008 Microprocessors Instruction Encoding
Q. Encode the following assembly language instruction to its equivalent machine value
addi r17, r18, 28
A. Utilizing material from Instruction Set Reference for addi instruction, the following steps can be used to accomplish this task.
addi r17,r18,
- r18 r17 28 addi
- 0x12 0x11 0x1c 0x
- 1 2 1 1 0 0 1 c 0 4
- 1 0010 1 0001 0000 0000 0001 1100 00 0100
- 1001 0100 0100 0000 0000 0111 0000 0100
- 9 4 4 0 0 7 0 4
- 0x94400704 is the machine code for addi r17,r18,
Explanation of steps above: Step (1.) Using the addi instruction format diagram and the assembler syntax definition, arrange the instruction in the diagram order. (2.) Encode the instruction fields in hexadecimal format. (3.) Space the hexadecimal digits to allow expansion to binary format. (4.) Encode values into binary format. (5.) Re-group instruction fields into groups of four bits each. (6.) Translate each group of four bits into equivalent hexadecimal representation. (7.) Resulting values represent machine instruction.
