CSE 380 Computer Operating Systems, Lecture notes of Operating Systems

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CSE 380

Computer Operating Systems

Instructor: Insup Lee University of Pennsylvania Fall 2003 Lecture Note: Virtual Memory (revised version)

Virtual Memory

 Recall: memory allocation with variable partitions requires mapping logical addresses to physical addresses  Virtual memory achieves a complete separation of logical and physical address-spaces  Today, typically a virtual address is 32 bits, this allows a process to have 4GB of virtual memory  Physical memory is much smaller than this, and varies from machine to machine  Virtual address spaces of different processes are distinct  Structuring of virtual memory  Paging: Divide the address space into fixed-size pages  Segmentation: Divide the address space into variable-size segments (corresponding to logical units)

Paging

 Physical memory is divided into chunks called page-frames (on Pentium, each page-frame is 4KB)  Virtual memory is divided into chunks called pages; size of a page is equal to size of a page frame  So typically, 2 20 pages (a little over a million) in virtual memory  OS keeps track of mapping of pages to page-frames  Some calculations:  10-bit address : 1KB of memory; 1024 addresses  20-bit address : 1MB of memory; about a million addresses  30-bit address : 1 GB of memory; about a billion addresses

Paging (2)

The relation between virtual addresses and physical memory addres- ses given by page table

Paging

 A virtual address is considered as a pair (p,o)  Low-order bits give an offset o within the page  High-order bits specify the page p  E.g. If each page is 1KB and virtual address is 16 bits, then low-order 10 bits give the offset and high-order 6 bits give the page number  The job of the Memory Management Unit (MMU) is to translate the page number p to a frame number f  The physical address is then (f,o), and this is what goes on the memory bus  For every process, there is a page-table (basically, an array), and page-number p is used as an index into this array for the translation

Page Table Entry

1. Validity bit: Set to 0 if the corresponding page is not in memory
2. Frame number  Number of bits required depends on size of physical memory
3. Protection bits:  Read, write, execute accesses
4. Referenced bit is set to 1 by hardware when the page is accessed: used by page replacement policy
5. Modified bit (dirty bit) set to 1 by hardware on write-access: used to avoid writing when swapped out

Design Issues

 What is the “optimal” size of a page frame?  Typically 1KB – 4KB, but more on this later  How to save space required to store the page table  With 20-bit page address, there are over a million pages, so the page-table is an array with over million entries  Solns: Two-level page tables, TLBs (Translation Lookaside Beffers), Inverted page tables  What if the desired page is not currently in memory?  This is called a page fault, and it traps to kernel  Page daemon runs periodically to ensure that there is enough free memory so that a page can be loaded from disk upon a page fault  Page replacement policy: how to free memory?

Multi-Level Paging

 Keeping a page-table with 2 20 entries in memory is not viable  Solution: Make the page table hierarchical  Pentium supports two-level paging  Suppose first 10-bits index into a top-level page-entry table T1 (1024 or 1K entries)  Each entry in T1 points to another, second-level, page table with 1K entries (4 MB of memory since each page is 4KB)  Next 10-bits of physical address index into the second-level page-table selected by the first 10-bits  Total of 1K potential second-level tables, but many are likely to be unused  If a process uses 16 MB virtual memory then it will have only 4 entries in top-level table (rest will be marked unused) and only 4 second-level tables

Translation Lookaside Buffer (TLB)

 Page-tables are in main memory  Access to main memory is slow compared to clock cycle on CPU (10ns vs 1 ns)  An instruction such as MOVE REG, ADDR has to decode ADDR and thus go through page tables  This is way too slow !!  Standard practice: Use TLB stored on CPU to map pages to page-frames  TLB stores small number (say, 64) of page-table entries to avoid the usual page-table lookup  TLB is associative memory and contains, basically, pairs of the form (page-no, page-frame)  Special hardware compares incoming page-no in parallel with all entries in TLB to retrieve page-frame  If no match found in TLB, standard look-up invoked

More on TLB

 Key design issue: how to improve hit rate for TLB?  Which pages should be in TLB: most recently accessed  Who should update TLB?  Modern architectures provide sophisticated hardware support to do this  Alternative: TLB miss generates a fault and invokes OS, which then decides how to use the TLB entries effectively. Page number Frame number Modified bit Protection bits

Hashed Page Tables

**Page number Offset Hash Page

Frame # Hash table Number of entries: Number of page frames PID PID**

Steps in Paging

 Today’s typical systems use TLBs and multi-level paging  Paging requires special hardware support  Overview of steps

1. Input to MMU: virtual address = (page p, offset o)
2. Check if there is a frame f with (p,f) in TLB
3. If so, physical address is (f,o)
4. If not, lookup page-table in main memory ( a couple of accesses due to multi-level paging)
5. If page is present, compute physical address
6. If not, trap to kernel to process page-fault
7. Update TLB/page-table entries (e.g. Modified bit)

Paging Summary

 How long will access to a location in page p take?  If the address of the corresponding frame is found in TLB?  If the page-entry corresponding to the page is valid?  Using two-level page table  Using Inverted hashed page-table  If a page fault occurs?  How to save space required to store a page table?  Two-level page-tables exploit the fact only a small and contiguous fraction of virtual space is used in practice  Inverted page-tables exploit the fact that the number of valid page-table entries is bounded by the available memory  Note: Page-table for a process is stored in user space

Page Replacement Algorithms

 When should a page be replaced  Upon a page fault if there are no page frames available  By pager daemon executed periodically  Pager daemon needs to keep free page-frames  Executes periodically (e.g. every 250 msec in Unix)  If number of free page frames is below certain fraction (a settable parameter), then decides to free space  Modified pages must first be saved  unmodified just overwritten  Better not to choose an often used page  will probably need to be brought back in soon  Well-understood, practical algorithms  Useful in other contexts also (e.g. web caching)