Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
This is solution manual for Digital Logic Design course. It was helpful for assignment Dr. Archan Singh gave us at Punjab Engineering College. It includes: Reset, D, Flip, Flop, Decoder, Synchronous, Multiplexer, IEEE, Time, Wave, Signals, Output
Typology: Exercises
1 / 6
This page cannot be seen from the preview
Don't miss anything!
8-2.
8-5.
0 1
S0 00
0
1
S1 01
0 1
0 1
S2 10
State: ST1 ST1 ST2 ST3 ST1 ST2 ST Z: 0 0 1 1 0 0
0
1
STD
STE Z
(^0) X 1
0
1
STB
STC Z
STA
0 1 X
Reset
8-8.
8-9.
8-12.
2 1
0 1 2 3
2
4
2 2
STA
STB STC STD STE
X Y
Y
Y DY
DY
DY
DY
DY
DY
Z
Reset
8-20. library IEEE; use IEEE.std_logic_1164.all; entity asm_820 is port ( A, B, C, CLK, RESET: in STD_LOGIC; Z: out STD_LOGIC ); end asm_820; architecture asm_820_arch of asm_820 is type state_type is (ST1, ST2, ST3); signal state, next_state : state_type; begin state_register: process (CLK, RESET) begin if RESET='1' then --asynchronous RESET active High state <= ST1; elsif (CLK'event and CLK='1') then --CLK rising edge state <= next_state; end if; end process; next_state_func: process (A, B, C, state) begin case (state) is when ST1 => if A = '0' then next_state <= ST1; else next_state <= ST2; end if; when ST2 => if ((B = '1') and (C = '1')) then next_state <= ST1; else next_state <= ST3; end if; when ST3 => next_state <= ST1; end case; end process; --Output Z only depends on the state and input 'B' output_func: process (B, state) begin case (state) is when ST1 => Z <= '0'; when ST2 => if (B = '1') then Z <= '1'; else Z <= '0'; end if; when ST3 => Z <= '1'; end case; end process; end asm_820_arch;
NOTE: State hex value 4 cooresponds to ST1, 2 to ST2 and 1 to ST3.
8-21. Errata: A, B, C should be ST1, ST2, ST3.
8-28.
8-32.
module asm_821 (CLK, RESET, A, B, C, Z) ; input CLK, RESET, A, B, C ; output Z ; reg [1:0] state, next_state; parameter ST1=2'b00, ST2=2'b01, ST3=2'b10, ST4=2'b11; reg Z; always @(posedge CLK or posedge RESET) begin if (RESET) //asynchronous RESET active High state <= ST1; else //use CLK rising edge state <= next_state; end //Next state function always @(A or B or C or state) begin case (state) ST1: next_state <= A? ST2: ST1; ST2: next_state <= (B && C)? ST1: ST3; ST3: next_state <= ST1; ST4: next_state <= ST1; // Next state ST1 is assigned to unused state ST4. endcase end //Output function always @(B or state) begin case (state) ST1: Z <= 1'b0; ST2: Z <= B? 1'b1: 1'b0; ST3: Z <= 1'b1; ST4: Z <= 0'b0; endcase end endmodule
NOTE: State hex value 0 cooresponds to ST1, 1 to ST2 and 2 to ST3.
8 7 4 3 0
NXTADD1NXTADD0 SEL DATAPATH
27 1817
28 bits/word
Total = 1024 words x 28 bits/word = 28,672 bits
a) Opcode = 8 bits , b) 16 bits c) 65,536 d) –32768 to +
