ECE 4514
Digital Design II
Spring 2008
Lecture 7:
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 7: Dataflow Modeling
Lecture 7:
Dataflow Modeling
A language Lecture
Patrick Schaumont
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Guidelines and tips
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Dataflow Modeling in Digital Design II: Understanding Net Assignments and Operators - Prof, Study notes of Electrical and Electronics Engineering
An overview of dataflow modeling in digital design ii, focusing on net assignments and operators. The differences between procedural and dataflow modeling, net declaration and continuous assignment, and various types of operators. It also includes examples and explanations of arithmetic, bitwise, reduction, logical, relational, and shift operators.
Typology: Study notes
Pre 2010
1 / 49
This page cannot be seen from the preview
Don't miss anything!
Related documents
Partial preview of the text
Download Dataflow Modeling in Digital Design II: Understanding Net Assignments and Operators - Prof and more Study notes Electrical and Electronics Engineering in PDF only on Docsity!
ECE 4514
Digital Design IISpring 2008
Lecture 7:
Lecture 7:
Dataflow Modeling
A^ language
Lecture
Patrick Schaumont
Today's topic ^ Dataflow Modeling
input^ input^^ module
input output^
output
Model with submodules
and gates=^ Structural
Model with alwaysand initial blocks
= BehavioralProcedural
Model withassign statements=^ BehavioralDataflow
Key differences with procedural code ^ Must assign nets (wires) instead of registers
module
nand(q,
a,^ b)
output
q; reg^ q; input
a,^ b;
module
nand(q,
a,^ b)
output
q; input
a,^ b;
Behavioral - Procedural
assign reg
Behavioral - Dataflowassign wire
input
a,^ b; always
@(a^
or^ b) q^ =^ ~(a
|^ b); endmodule
assign
q^ =^
~(a^ |
b);
endmodule
Procedural Assignment
Continuous^ Assignment
Key differences with procedural code ^ Must assign nets (wires) instead of registers
module
nand(q,
a,^ b)
output
q; reg^ q; input
a,^ b;
module
nand(q,
a,^ b)
output
q; input
a,^ b;
Behavioral - Procedural
assign reg
Behavioral - Dataflowassign wire
input
a,^ b; always
@(a^
or^ b) q^ =^ ~(a
|^ b); endmodule
assign
q^ =^
~(a^ |
b);
endmodule
Note that both will end up as the same hardware
Assign two wires^ Concurrent Assign statements
q
module
nand(q1,
q2,^
a,^ b)
output
q1,^
q2; input
a,^ b;
Patrick SchaumontSpring 2008
a b^
q
input
a,^ b; assign
q1^ =
~(a^
|^ b);
assign
q2^ =
~(a^
&^ b);
... endmodule
Assign two wires
q
module
nand(q1,
q2,^
a,^ b)
output
q1,^
q2;
Single Assign statement with twoindependent assignments
Patrick SchaumontSpring 2008
a b^
q
output
q1,^
q2; input
a,^ b; assign
q1^ =
~(a^
|^ b), q2^ =^
~(a^ &
b);
... endmodule
Delay in continuous assignments^ module
nand(q,
a,^ b)
output
q; input
a,^ b; wire^
n; assign
#^
n^ =^ ~(a
|^ b);
... endmodule
Changes to n take an
inertial delay
of 10 units
module
nand(q,
a,^ b)
output
q; input
a,^ b; wire^
n; assign
n^ =^
~(a^ |
b);
... endmodule
Changes to n take an
inertial delay
of 10 units for rising edges and15 units for falling edges
Delay in continuous implicit assignments^ module
nand(q,
a,^ b)
output
q; input
a,^ b; wire^
#10^ n
=^ ~(a
|^ b);
... endmodule
Changes to n take an
inertial delay
of 10 units
module
nand(q,
a,^ b)
output
q; input
a,^ b; wire^
#10^ n; assign
#^
n^ =^ ~(a
|^ b);
... endmodule
Changes to n take an
inertial delay
of 20 units
Operand Types
assign {c0, d} = a + b;
Right-Hand Side
Left-Hand Side
=
nets (wire)
nets (wire)variable (reg)parametersnumbersfunction call
Operand Bit-select and Part-select
wire [7:0] n;
n[3:0] n[3]
Bit 3, 2, 1, 0 Bit 3
n[3] n[x]n[3 +:2]
Bit 3 X Bit 3, 4
Operand Types
Right-Hand Side
Left-Hand Side
=
-^ net •^ net bit-select or part-select •^ indexed net •^ indexed net bit - select or part - select
'net' can be
-^ indexed net bit
- select or part
- select -^ concatenated net
wire [7:0] n[0:99]; {n[15][0:3], n[2]} = 5_bit_expr;
Operators ^ Arithmetic ^ Bitwise ^ Reduction ^ Logical ^ Relational
^ Relational ^ Shift ^ Selection ^ Concatenation & Replication
General Rules for Arithmetic Precision ^ Assignments will not loose precision if the target islarge enough^
If a and b are 15 bit, and c is 16 bit, then c = a + b will notloose precision ^ Assignments will loose precision if the target is notlarge enough^
If a and b are 15 bit, and c is 8 bit, then c = a + b captures the ^ If a and b are 15 bit, and c is 8 bit, then c = a + b captures the^ 8 lsb of the addition Standalone expressions
may
loose precision
^ If a and b are 15 bit, then the standalone expression a + buses 15 bit (max wordlength over a and b), and thus mayloose precision ^ Standalone expressions occur in some system calls like e.g.$display("a+b=%h", a+b);