Download Digital ASIC Design Guide by Don Bouldin, ECE 551, UT, Fall 2001 - Prof. Donald Bouldin and more Exams Digital Systems Design in PDF only on Docsity!
© 2001 -- Don Bouldin
DESIGNING DIGITAL ASICS
ECE 551
FALL 2001
Don Bouldin, Ph.D., P.E.
Prof. of Electrical & Computer Engineering
University of Tennessee
TEL: (865)-974-
FAX: (865) -974-
SCHEMATIC AND OR
AND
architecture behavior of control isHDL if left_paddle thenn_state <= hit_state elsif n_state <= miss_stateend if;
PLACE & ROUTE PHYSICAL LAYOUT
SYNTHESIS
© 2001 -- Don Bouldin
DESIGN IMPLEMENTATION
• Design Flow
• Prototyping Tips
• Basic Built-In Self-Test
• Debouncing External Switches
• Filtering an Input to Produce a Single Pulse
• Hierarchy with Submodule Components
• Synchronizing External Inputs
© 2001 -- Don Bouldin
DESIGN FLOW
© 2001 -- Don Bouldin
DETERMINE SYSTEM I/O REQUIREMENTS
DECOMPOSE EACH LEVEL
INTO 7+/-2 SUBMODULES
SYNTHESIZE AND SIMULATE EACH
SUBMODULE AND THEN INTEGRATE THEM
© 2001 -- Don Bouldin
GENERATE THE PHYSICAL LAYOUT
© 2001 -- Don Bouldin
DESIGN STEPS (part 1)
1. Analyze the requirements of the application.
2. Develop the initial architectural specifications.
3. Decompose the design into 7+/ -2 manageable blocks
at each level of the hierarchy from top to bottom.
4. Develop structural VHDL for each level to show the
interconnections of submodules.
5. Develop the VHDL code for each submodule.
© 2001 -- Don Bouldin
DESIGN STEPS (part 2)
6. Compile and test each VHDL submodule individually
(You may find it easier to enter the design bottom-up).
7. Integrate previously tested submodules and test all of
them together at each level.
8. Generate the physical layout of the entire design.
9. Perform a post-layout simulation of the entire design.
10. Download the configuration file to the prototype
board to demonstrate the working design.
© 2001 -- Don Bouldin
DESIGN FLOW
ALTERA PROTOTYPING BOARD
BASIC BUILT-IN SELF-TEST
• Downloading bist_alt ensures the integrity of the
connection between the CPU and the Altera
prototyping board AND then checks one input switch
and both 7 -segment displays.
• More thorough checks could be added to ensure the
integrity of the board I/O for a specific project.
© 2001 -- Don Bouldin
debounce.vhd (part 1)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- Debounce Pushbutton: Filters out mechanical switch bounce for around 40Ms.
ENTITY debounce IS
PORT(pb, clock_100Hz : IN STD_LOGIC;
pb_debounced : OUT STD_LOGIC);
END debounce;
© 2001 -- Don Bouldin
debounce.vhd (part 2)
ARCHITECTURE a OF debounce IS
SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- Debounce clock should be approximately 10ms or 100Hz
PROCESS
BEGIN
WAIT UNTIL (clock_100Hz'EVENT) AND (clock_100Hz = '1');
-- Use a shift register to filter switch contact bounce
SHIFT_PB(2 DOWNTO 0) <= SHIFT_PB(3 DOWNTO 1);
SHIFT_PB(3) <= NOT PB;
IF SHIFT_PB(3 DOWNTO 0)="0000" THEN
PB_DEBOUNCED <= '0';
ELSE
PB_DEBOUNCED <= '1';
END IF;
END PROCESS;
END a;
© 2001 -- Don Bouldin
BEHAVIOR OF debounce.vhd
CLOCK PB SHIFT_PB PB_DEBOUNCED
© 2001 -- Don Bouldin
FILTERING AN INPUT TO
PRODUCE A SINGLE PULSE
A Circuit Can Be Implemented
to Produce Only a Single Pulse
An External Pushbutton Switch May
Be Held Down For Multiple Clock Ticks
onepulse.vhd (part 1)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- Single Pulse circuit
-- the output will go high for only one clock cycle
ENTITY onepulse IS
PORT(PB_debounced, clock : IN STD_LOGIC;
PB_single_pulse : OUT STD_LOGIC);
END onepulse;
onepulse.vhd (part 2)
ARCHITECTURE a OF onepulse IS
SIGNAL PB_debounced_delay, Power_on : STD_LOGIC;
BEGIN
PROCESS (Clock)
BEGIN
WAIT UNTIL (CLOCK'event) AND (CLOCK='1');
-- Power_on will be initialized to '0' at power up
IF Power_on='0' THEN
-- This code resets the critical signals once at power up
PB_single_pulse <= '0';
PB_debounced_delay <= '1';
Power_on <= '1';
ELSE
© 2001 -- Don Bouldin
onepulse.vhd (part 3)
-- A single clock cycle pulse is produced when the switch is hit
-- No matter how long the switch is held down
-- The switch input must already be debounced
IF PB_debounced = '1' AND PB_debounced_delay = '0' THEN
PB_single_pulse <= '1';
ELSE
PB_single_pulse <= '0';
END IF;
PB_debounced_delay <= PB_debounced;
END IF;
END PROCESS;
END a;
© 2001 -- Don Bouldin
HIERARCHY WITH SUBMODULE
COMPONENTS
clock_25Mhz
clk_div
pb
clock_100Hz
clock_1Mhz
prescalar
debounce1 single_pulse
pb_debounced pb1_single_pulse
debounce onepulse
© 2001 -- Don Bouldin
hierarch.vhd (part 1)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY hierarch IS PORT (clock_25Mhz, pb1 : IN STD_LOGIC; pb1_single_pulse : OUT STD_LOGIC); END hierarch; ARCHITECTURE a OF hierarch IS -- Declare internal signals needed to connect submodules SIGNAL clock_1MHz, clock_100Hz, pb1_debounced : STD_LOGIC; -- Use Components to Define Submodules and Parameters COMPONENT debounce PORT(pb, clock_100Hz : IN STD_LOGIC; pb_debounced : OUT STD_LOGIC); END COMPONENT;
© 2001 -- Don Bouldin
hierarch.vhd (part 2)
COMPONENT onepulse PORT(pb_debounced, clock : IN STD_LOGIC; pb_single_pulse : OUT STD_LOGIC); END COMPONENT;
COMPONENT clk_div PORT(clock_25Mhz : IN STD_LOGIC; clock_1MHz : OUT STD_LOGIC; clock_100KHz : OUT STD_LOGIC; clock_10KHz : OUT STD_LOGIC; clock_1KHz : OUT STD_LOGIC; clock_100Hz : OUT STD_LOGIC; clock_10Hz : OUT STD_LOGIC; clock_1Hz : OUT STD_LOGIC); END COMPONENT;
hierarch.vhd (part 3)
BEGIN
-- Use Port Map to connect signals between components in the hierarchy
debounce1 : debounce PORT MAP (pb => pb1, clock_100Hz => clock_100Hz,
pb_debounced => pb1_debounced);
prescalar : clk_div PORT MAP (clock_25Mhz => clock_25Mhz, clock_1MHz =>
clock_1Mhz, clock_100hz => clock_100hz);
single_pulse : onepulse PORT MAP (pb_debounced => pb1_debounced, clock =>
clock_1MHz,
pb_single_pulse => pb1_single_pulse);
END a;
HIERARCHY WITH SUBMODULE
COMPONENTS
clock_25Mhz
clk_div
pb
clock_100Hz
clock_1Mhz
prescalar
debounce1 single_pulse
pb_debounced pb1_single_pulse
debounce onepulse
