VHDL Synthesis: Compiling Netlists for FPGA and ASIC Design, Study notes of Engineering

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COE 1502

Design Synthesis

Synthesis Background

 Idea:

– “Compile” VHDL into a cell-level netlist

 A netlist is a graph

• Vertices represent cells (such as gates, latches, etc.)
• Edges represent interconnection wires

 To do this, we need

• VHDL
• A technology cell library

– Place-and-route netlist onto FPGA/ASIC

 To do this, we need

• Netlist
• CLB specification and routing matrix (FPGA)

 Output is FPGA routing bitmap

Netlists

 Synthesis tool output format is a text EDIF netlist

 Example:

port port port

OR

AND

port

A

B

C

D

E

instance OR2 as ix

instance AND2 as ix

ix1 A B D

ix3 D C E

Note that AND and OR2 are technology cells

Netlists

 Actual EDIF output:

(edif example (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timestamp 2003 01 23 17 13 48) (program "LeonardoSpectrum Level 3" (version "2002b.21")) (author "Exemplar Logic Inc"))) (external PRIMITIVES (edifLevel 0) (technology (numberDefinition )) (cell OR2 (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port (rename p0 "in[0]") (direction INPUT)) (port (rename p1 "in[1]") (direction INPUT)) (port out (direction OUTPUT))))) (cell AND2 (cellType GENERIC) (view INTERFACE (viewType NETLIST) (interface (port (rename p2 "in[0]") (direction INPUT)) (port (rename p3 "in[1]") (direction INPUT)) (port out (direction OUTPUT)))))) (library alu (edifLevel 0) (technology (numberDefinition )) (cell example (cellType GENERIC) (view struct (viewType NETLIST) (interface (port A (direction INPUT)) (port B (direction INPUT)) (port C (direction INPUT)) (port E (direction OUTPUT))) (contents (instance ix1 (viewRef INTERFACE (cellRef OR (libraryRef PRIMITIVES )))) (instance ix3 (viewRef INTERFACE (cellRef AND (libraryRef PRIMITIVES )))) (net A (joined (portRef A ) (portRef p0 (instanceRef ix1 )))) (net B (joined (portRef B ) (portRef p1 (instanceRef ix1 )))) (net C (joined (portRef C ) (portRef p3 (instanceRef ix3 )))) (net E (joined (portRef E ) (portRef out (instanceRef ix3 )))) (net D (joined (portRef out (instanceRef ix1 )) (portRef p2 (instanceRef ix3 )))))))) (design example (cellRef example (libraryRef alu ))))

ALU Wrapper Structure

Design Wrapper - Included as VDHL code and synthesized w/your design

Pinout Wrapper - pre-synthesized and included during place and route

ALU Design Wrapper

Your ALU Host app registers Host interface Analyzer Data

Preparing for Synthesis

 Copy the wrapper design from COElib to

your project lib

 Make sure that the ALU instance in the

wrapper maps to your design

Running synthesis