HDL Introduction and ASIC Design Approach using VHDL, Slides of Computer Science

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Table of contents

• HDL Introduction
• Structured Design Concepts
• Basic Features of VHDL
• Design Process Highlights

HDL

Introduction

Modern ASIC design approach

• ASIC – Application Specific Integrated Circuit
• Modeling system should be designed and described in the highest abstraction level possible
• Simulation and testing at high abstraction level
• Conversion of the modeled system into the low abstraction level model (gate, circuit, silicon level) using sophisticated synthesis tools
• Key point – CAD (Computer Aided Design)

HDL Introduction

Modern ASIC design approach

• HDLs (Hardware Description Languages) are used for system description at the high abstraction level

HDL Introduction

Design

Description Simulation & Testing

Gate Level Model

Conversion

RTL Model HIGH ABSTRACTION LEVEL LOW ABSTRACTION LEVEL

Structural Design

Concepts

The abstraction hierarchy

• The abstraction hierarchy can be expressed in two domains: structural domain, behavioral domain
• Structural domain – component model is described in terms of an interconnection of more primitive components
• Behavioral domain – component model is described by defining its input/output response
• VHDL is used for both structural and behavioral description
• Six abstraction hierarchy levels of detail commonly used in design: silicon, circuit, gate, register, chip and system

Structural Design Concepts

Design process

• The design cycle steps can be carried out automatically in all stages except the first that is currently an active area of research
• VHDL tools are used for algorithmic synthesis

Structural Design Concepts

Design tools

• Editors – textual (circuit level – SPICE gate, register, chip – VHDL) or graphic (used at all levels)
• Simulators – stochastic (system level)

or deterministic (all levels above the silicon level)

• Checkers and Analyzers – employed at all levels, used for example

Structural Design Concepts

Design entities

• In VHDL a logic circuit is represented as a design entity
• A design entity consists of two different VHDL types of description:

(1) Interface description (reserved word is entity ) (2) One or more architectural bodies (reserved word is architecture )

Basic Features of VHDL

D Q D FF CLK R

Designed digital device

entity D_FF defining D FF interface (ports) architecture of D_FF specifying the behavior of the entity VHDL representation Docsity.com

Entity

• The entity part provides system’s interface specification as seen from the outside and is generally comprised of:

(1) Parameters (such as bus width or max clock frequency) (2) Connections (system input and output ports)

Basic Features of VHDL

Processes

• Process is another major modeling element in VHDL:

ProcessLabel begin : ProcessName ( sensitivity_list_of_signals ) is end process^ -- sequential statements; ;

• Processes are used inside architectural bodies, specifying entity behavioral in algorithmic way

Basic Features of VHDL

Sequential and parallel processing

• The statements within process are performed sequentially
• The statements within architectural body are performed concurrent
• Sequential and concurrent combination is called VHDL duality and it presents powerful mechanism

Basic Features of VHDL

Design Process

Highlights

MAC (Multiply Accumulator) unit

• Incoming part is based on MAC unit design and synthesis as part of Computer VLSI Systems , subject lectured by Dr. Veljko Milutinovic
• Basic specification elements of MAC unit:

(1) purpose – hardware support for numerous succeeding

Design Process Highlights