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NAND Gate Latch Operation: Setup and Hold Time, Lecture notes of Digital Systems Design
The operation of a NAND gate latch with focus on setup and hold time. It provides detailed cases of the latch behavior when input D changes and clock CLK is toggled. useful for understanding the concepts of setup and hold time in digital electronics.
Typology: Lecture notes
2019/2020
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BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
1 0 O
No Change
Not Reccomm
S R Q
NAND Based Latch
S
R
Q
Q’
A B Case I:
- D = 0, CLK = 0
- D = 0 => B = 1
- CLK = 0 => R =1, S = 1
- Case II: D = 1, CLK = 0
- CLK = 0 => R =1, S = 1
- D = 1, R = 1 => B = 0
- B = 0, S = 1 => A = 1
- ASRB = 1110
- SR = 11 => No change
A B Case I:
- D = 0, CLK = 0
- D = 0 => B = 1
- CLK = 0 => R =1, S = 1
- B = 1, S = 1 => A = 0
- ASRB = 0111
- Case II: D = 1, CLK = 0
- CLK = 0 => R =1, S = 1
- D = 1, R = 1 => B = 0
- B = 0, S = 1 => A = 1
- ASRB = 1110
- SR = 11 => No change
In case I make CLK= i.e., ASRB= A B
In case I make CLK= i.e., ASRB=
- D=0 => B=
- A=0 => S= A B
In case I make CLK= i.e., ASRB=
- D=0 => B=
- A=0 => S=
- S=1,B=1,CLK=1 => R=
- SR=10 => RESET
- ASRB= Only R has changed here after one gate delay. . A B
In case I make CLK= i.e., ASRB=
- D=0 => B=
- A=0 => S=
- S=1,B=1,CLK=1 => R=
- SR=10 => RESET
- ASRB= Only R has changed here after one gate delay. If D changes after R has stabilized there will be no effect on output. . A B
A B Case II:
- D = 1, CLK = 0
- CLK = 0 => R =1, S = 1
A B Case II:
- D = 1, CLK = 0
- CLK = 0 => R =1, S = 1
- D = 1, R = 1 => B = 0
- B = 0, S = 1 => A = 1
In case II make CLK = 1
- ASRB = 1110
- R=1, D=1 => B=
- B=0, => A= A B
In case II make CLK = 1
- ASRB = 1110
- R=1, D=1 => B=
- B=0, => A=
- A=1,CLK=1 => S=0 =>R=
- SR=01 => SET
- ASRB= A B
Going from D=1, CLK=0 to D=0, CLK = 1 ASRB=
- D=0 => B= A B
Going from D=1, CLK=0 to D=0, CLK = 1 ASRB=
- D=0 => B=
- CLK=1, A=1 => S= A B