ELC403 - Exercise I
1-Sketch a transistor-level schematic for a CMOS 4-input NOR gate.
2- Sketch a transistor-level schematic for a CMOS 4-input NAND gate.
3-Sketch a transistor-level schematic for a single-stage CMOS logic gate
for each of the following functions:
4- Sketch a transistor-level schematic of a CMOS 2-input XOR gate. You
may assume you have both true and complementary versions of the
inputs available.
