Digital Electronics - 2003 2004 Exam - Electrical Engineering, Exams of Electrical Engineering

Professor Miller, Manchester Metropolitan University, Electrical Engineering, Digital Electronics, 2003 2004 Exam, digital system, output, gate, binary value, logic level, active high, edge triggered, flip flop, karnaugh map, stable state, odd parity, circuit, PPI, I/O.

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S308 05/10/04
THE MANCHESTER METROPOLITAN UNIVERSITY
FACULTY OF SCIENCE AND ENGINEERING
DEPARTMENT OF ENGINEERING AND TECHNOLOGY
SESSION 2003/2004
Examination for the
BEng (HONS) ELECTRICAL ENGINEERING
HND ELECTRONIC ENGINERING
YEAR/STAGE ONE
UNIT 64EE1103 : DIGITAL ELECTRONICS
Tuesday 25 May 2004
2.00 pm to 4.00 pm
Instructions to Candidates
Answer FOUR questions.
Separate answer sheets are provided for use with Questions 1, 2 and 3. These should be
handed in with your answer books if you choose to answer these questions.
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S308 05/10/

THE MANCHESTER METROPOLITAN UNIVERSITY

FACULTY OF SCIENCE AND ENGINEERING

DEPARTMENT OF ENGINEERING AND TECHNOLOGY

SESSION 2003/

Examination for the BEng (HONS) ELECTRICAL ENGINEERING HND ELECTRONIC ENGINERING YEAR/STAGE ONE

UNIT 64EE1103 : DIGITAL ELECTRONICS

Tuesday 25 May 2004

2.00 pm to 4.00 pm

Instructions to Candidates

Answer FOUR questions.

Separate answer sheets are provided for use with Questions 1, 2 and 3. These should be handed in with your answer books if you choose to answer these questions.

  1. A digital system is defined by the truth table below. It has four inputs (S3,S2,S1,S0) and two outputs (X,Y).

S3 S2 S1 S0 X Y

0 0 0 1 1 X

0 0 1 1 1 X

0 1 0 1 1 X

0 1 1 1 1 X

(a) Label the Karnaugh maps shown in figure 1. [5]

(b) Map each output. [5]

(c) Derive the minimised equations for each output. [10]

(d) Complete the circuit diagram (figure 2) using the minimum number of gates. [5]

he data would be changing at the same time as the clock it is not possible to predict the Q output, it could be logic one or a logic zero

  1. An RS flip flop, shown below, is initially at the condition R=S =0 AND P=Q=1.

The inputs R and S are then changed in the sequence shown the table below.

SEQUENCE R S

initially 0 0 1 1 0 2 1 1 3 0 1 4 0 0

(a) Label the Karnaugh map (figure 4) and complete for QP. [10]

(b) Show the input sequence on the Karnaugh map. [10]

(c) Identify the stable states that the sequence passes through. [5]

R

S

Q

P

p

q

  1. (a) An odd parity system receives the following code groups:

FFFFh, FFFEh, 0001h.

The following code groups are BCD with even parity bits to the left of the MSB.

10001BCD, 00000BCD, 11001BCD

(b) Determine which of the six groups are in error. [6]

(c) Design circuits for the following two functions describing in detail how each works. (i) A comparator circuit that compares two binary numbers of two bits each and produces a HIGH output if the two numbers are equal. [7] (ii) A four bit Binary to Gray code converter. [7]

(d) If an X-OR gate is not available for a particular circuit show how other basic logic gates could be applied to produce the same function. [5]