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Lab 0: Introduction to FPGAs using Quartus Prime Lite 20.
This lab is designed to familiarize you with using many of the common aspects of the Quartus II software through a complete design phase. You will create a new project, create a new SystemVerilog file, compile the design, plan and manage I/O assignments, and program a design onto the Altera DE 0 Development Board. Each logic circuit, or sub-circuit, being designed with Quartus II software is called a project. The software works on one project at a time and keeps all information for that project in a single directory (folder) in the file system. To begin a new logic circuit design, the first step is to create a directory to hold its files. To hold the design files for this tutorial, we will use a directory “Lab 0 ”. The running example for this tutorial is a simple circuit for two- way light control. Figure 1 Main Quartus Prime Display
1.1. Creating a Project:
To start working on a new design we first have to define a new design project. Quartus II software makes the designer’s task easy by providing support in the form of a wizard. Create a new project as follows:
1. Select File → New Project Wizard to reach the window in Figure 2 (a). Then click on Next button to reach a
window which asks for the name and directory of the project. Set the working directory to be Lab1; of course, you can use some other directory name of your choice if you prefer. The project must have a name, which is usually the same as the top-level design entity that will be included in the project. Choose lab1 as the name for both the project and light as the name for the top-level entity, as shown in Figure 2 (b). Press Next.
Figure 2 New Project Creation Wizard in Quartus II
2. The wizard makes it easy to specify which existing files (if any) should be included in the project. Since we do not have any existing files, click Next, which leads to the window in Figure 3 The wizard can include user- specified design files. Choose the device family and a specific device. (a) (b) Figure 3 The wizard can include user-specified design files. Choose the device family and a specific device.
- We have to specify the type of device/board in which the designed circuit will be implemented. Change to board tab in the window and select DE0-CV as the board name. Then, remember to deselect “Create top- level design file”. (You can enter this device name 5CEBA4F23C7 into Name Filter text box). Press Next, which opens the window in Figure 4. Click Next. (a) (b)
Figure 6 The light controller circuit The required circuit is described by the SystemVerilog code in Figure 7 Error! Reference source not found.. Note that the SystemVerilog entity is called light to match the name given in Error! Reference source not found. Figure 5 , which was specified when the project was created. This code can be typed into a file by using any text editor that stores ASCII files, or by using the Quartus II text editing facilities. While the file can be given any name, it is a common designers’ practice to use the same name as the name of the top-level SystemVerilog entity. The file name must include the extension .sv, which indicates a SystemVerilog file. So, we will use the name light.sv.
Select File → New to get the window in Figure 8 Error! Reference source not found. , choose SystemVerilog
File, and click OK. This opens the Text Editor tab. Enter your SystemVerilog description into the tab and save the file. Remember that your file name should be as same as the SystemVerilog entity name, which is light in this case. Save your file with an extension .sv. Put a checkmark in the box Add file to current project. Figure 8 Choose to prepare a SystemVerilog file to get a Text Editor tab
1.3. Compiling the Designed Circuit:
The SystemVerilog code in the file light.vhd is processed by several Quartus II tools that analyze the code, synthesize the circuit, and generate an implementation of it for the target chip. These tools are controlled by the application program called the Compiler.
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f x 1 x 2 f 0 0 0 0 1 1 1 0 1 1 1 0 module light(input x1,x2, output f); assign f = (x1 & ~x2) | (~x1 & x2) ; endmodule: light Figure 7 SystemVerilog Code for the circuit in Figure 6 The light controller circuit
Run the Compiler by selecting Processing → Start Compilation (see Figure 9 Error! Reference source not found. ),
or by clicking on the toolbar icon that looks like a purple triangle. As the compilation moves through various stages, its progress is reported in a window on the left side of the Quartus II display. Successful (or unsuccessful) compilation is indicated in a pop-up box. Figure 9 Design compilation window. Acknowledge it by clicking OK, which leads to the Quartus II display in Figure 10 Error! Reference source not found.. In the message window, at the bottom of the figure, various messages are displayed. In case of errors, there will be appropriate messages given. Figure 10 Display after a successful compilation.
your pin assignment window will be similar to Figure 13. Figure 13 The complete pin assignment.
1.5. Simulating the Designed Circuit:
Before implementing the designed circuit in the FPGA chip on the DE0 board, it is prudent to simulate it to ascertain its correctness. Quartus II software too includes a simulation tool that can be used to simulate the behaviour of a designed circuit. Before the circuit can be simulated, it is necessary to create the desired waveforms, called test vectors, to represent the input signals. It is also necessary to specify which outputs, as well as possible internal points in the circuit, the designer wishes to observe. The simulator applies the test vectors to a model of the implemented circuit and determines the expected response. We will use the Quartus II Waveform Editor to draw the test vectors, as follows:
1. Open the Waveform Editor window by selecting File → New , which gives the window shown in Figure 14 Error!
Reference source not found. (a). Choose University Program VWF under the section Verification/Debugging and click OK. Figure 14 The Waveform Editor window
- The Waveform Editor window is also depicted in Figure 14 Error! Reference source not found. (b). Save the file using the default name otherwise a software error occurs (seems to be a bug in the software version). Set the desired simulation to run from 0 to 200 ns by selecting Edit → End Time and entering 200 ns in the dialog box that pops up. Selecting View → Fit in Window displays the entire simulation range of 0 to 200 ns in the window. You may wish to resize the window to its maximum size.
3. Next, we want to include the input and output nodes of the circuit to be simulated. Click Edit → Insert →
Insert Node or Bus to open the window in Figure 15 Error! Reference source not found.. It is possible to type the name of a signal (pin) into the Name box, but it is easier to click on the button labeled Node Finder to open the window in Figure 15 Error! Reference source not found.. Error! Reference source not found. The Node Finder utility has a filter used to indicate what type of nodes are to be found. Since we are interested in input and output pins, set the filter to Pins: all. Click the List button to find the input and output nodes as indicated on the left side of the figure. Figure 15 The Insert Node or Bus dialogue and selecting nodes to insert into the waveform Editor (a) (b)
the Selection Tool, which is activated by selecting the icon in the toolbar, or the Waveform Editing Tool, which is activated by the icon.
- To simulate the behavior of a large circuit, it is necessary to apply a sufficient number of input valuations and observe the expected values of the outputs. In a large circuit the number of possible input valuations may be huge, so in practice we choose a relatively small (but representative) sample of these input valuations. However, for our tiny circuit we can simulate all four input valuations given in
- We will use four 50-ns time intervals to apply the four test vectors. Figure 17 Waveform Window to setup test values
- We can generate the desired input waveforms as follows. Say we want to set x1 to 1 in the time interval 0 to 50ns. Highlight that time interval and right click. Then, from the menu you can select value → Forcing High (1). Commands are available for setting a selected signal to 0, 1, unknown (X), high impedance (Z), don’t care (DC), inverting its existing value (INV), or defining a clock waveform.
- Similarly, enter values for x1 and x2 to reach a window as shown in Figure 18 Error! Reference source not found.. Observe that the output f is displayed as having an unknown value at this time, which is indicated
by a hashed pattern; its value will be determined during simulation. Save the file. Figure 18 Setting of test values
- Functional Simulation: The simplest way is to assume that logic elements and interconnection wires in the FPGA are perfect, thus causing no delay in propagation of signals through the circuit. This is called functional simulation. To perform the functional simulation, select simulation → Run Functional Simulation. If get an error as shown in Figure 19 , on the simulation waveform editor, go to simulation → simulations options to get the window Figure 19 (b). Delete - novopt option from line 5 as shown, save and carry on with “Run Functional Simulation”. Figure 19 A possible error message and the fix for that
Configuring the FPGA in JTAG Mode: Figure 21 JTAG configuration setup Figure 21 illustrates the JTAG configuration setup. To download a configuration bit stream into the Cyclone III FPGA, perform the following steps:
- Ensure that power is applied to the DE0-CV board
- Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW10) to the RUN position (See Figure 21 Error! Reference source not found. )
- Connect the USB cable provided to the USB Blaster port on the DE0-CV board
- The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the .sof filename extension.
- Select Tools → Programmer to reach the window in. Here it is necessary to specify the programming hardware and the mode that should be used. If not already chosen by default, select JTAG in the Mode box. Also, if the USB-Blaster is not chosen by default, press the “Hardware Setup...” button and select the USB-Blaster in the window that pops up.
Figure 22 The Programmer window
- Note also that the device selected is 5CEBA4F23, which is the FPGA device used on the DE 0 - CV board. Click on the Program/Configure check box, as shown in Figure 22 Error! Reference source not found..
- Now, press Start in the window in Figure 23. An LED on the board will light up when the configuration data has been downloaded successfully. There is a progress indicator in top right hand corner of the window and it will become green when it has successfully programmed the FPGA. If you see an error reported by Quartus II software indicating that programming failed, then check to ensure that the board is properly powered on. Figure 23 Programmer window after successful programming if the USB-Blaster is not chosen by default
