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TH E MANCH ESTER M ETR O PO LITAN UNIVER SITY
FACULTY O F SCIENCE AND ENGINEER ING
D EPA R TMENT O F ENGINEER ING AND TECH NO LO GY
SESSIO N 2000/
Exam ination for th e BEng (H O NS) ELECTR ICA LAND ELECTR O NIC ENGINEER ING (FULL- TIME/SANDWICH ) YEA R TW O BEng (H O NS) ELECTR O NIC ENGINEER ING YEA R O NE BEng (H O NS) ELECTR ICA LAND ELECTR O NIC ENGINEER ING (PA R T-TIME) YEA R O NE
UNIT 64EE2017: D IGITALELECTR O NICS II
W ednesday 30 May 2001
9 .30 am to 10.30 am
Instructions to Candidates
A nsw er TW O questions.
MAXIM MAX520/521 data sh eet attach ed.
06/09 /02 continued
- R efer to th e attach ed MAX520/521 data sh eet.
(a) State th e difference b e tw een th e MAX 520 and 521, th e function of th e MAX 520 device, and any advantages th e MAX 520 h as over th e MAX521. [2]
(b ) D e scrib e th e MAX520ACPE device pack age and allits pin connections. [8]
(c) State th e m ain difference b e tw een th e MAX520/521_C, MAX520/521_E, and th e MAX520/521_MJE parts, and state a typicalplace of use for each part. [4]
(d) State th e input h igh and input low voltage specifications for th e serialdata and clock signals, for b oth m inim um and m axim um values of VD D. [2]
(e) State th e function of th e inputs A D 0-2, sh ow w ith a suitab le diagram h ow th ey are used, and describ e h ow th e devices are selected. A lso state w h y th e address bit A D 2 in Figures 5 and 7 is stated as 0 or A D 2. [9 ]
06/09 /02 continued
- (a) Figure Q 3a sh ow s th e ph ysicallayout of one data b it of a m icroprocessor bus system. State th e prob lem s th at m ay occur w ith th is layout and sh ow h ow th e layout sh ould b e ch anged to resolve th ese problem s. [4]
Figure Q 3a
(b ) Long lines are often term inated w ith a spilt term ination of 220/330 oh m s. State w h y term ination is needed, calculate th e totalresistance of th is com b ination 220/330 oh m s and, giving your reasons, say w h y th is is a good com b ination.
State th e quiescent voltage on th e line, and if th is is w ith in th e CMO S input voltage levels. If not, say w h y th e system stillw ork s. [6]
Calculate th e reflection co-efficient for th is arrangem ent for a 100 oh m line and w h at oth er com ponents are needed and w h y th ey are added. [4]
(c) Figure Q 3b sh ow s a voltage supply connected to tw o inverters. Using suitab le diagram s sh ow h ow th e current flow s from th e supply th rough th e inverters and returns via th e ground connection for th e driver output in b oth th e h igh and low states. [6]
5V G
Figure Q 3b State w h at you conclude ab out th e direction of th e current flow around th e PCB, and th e positioning of th e supply. [5]
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- R efer to MAX 520 data sh eet.
Figure 1 on th e MAX 520 data sh eet sh ow s th e serialinterface tim ing diagram.
State:
(a) W h at indicates a STA R T condition?
(b ) H ow is a low data b it clock ed into th e MAX 520?
(c) H ow is a h igh data b it clock ed into th e MAX 520?
(d) W h at indicates a STO P condition? [6]
(e) W rite dow n a sim ple flow ch art or pseudo-code including tim ings, th at w ill clock :
(i) a h igh data b it; (ii) a low data b it.
into th e device. [12]
(f) Consequently w rite a sim ple flow ch art, or list of com m ands to set th e D A C outputs as sh ow n in Figure 7 of th e data sh eet. Th is sh ould address only th e first D A C0, setting it to h alf scale, assum e th at th e slave address is 2, and include th e STO P condition. [7]
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