Logic Circuits Exam Paper: Marking Scheme and Questions, Exams of Digital Logic Design and Programming

Digital Logic Design and Programming

Typology: Exams

2019/2020

Uploaded on 06/12/2023

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Philadelphia University
Faculty of Engineering
Marking Scheme
Exam Paper
BSc CE
Logic Circuits (630211)
Final Exam First semester Date: 28/01/2020
Section 1
Weighting 40% of the module total
Lecturer: Dr. Qadri Hamarsheh
Coordinator: Dr. Qadri Hamarsheh
Internal Examiner: Eng. Anis Nazer
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Philadelphia University

Faculty of Engineering

Marking Scheme

Exam Paper

BSc CE

Logic Circuits ( 630211 )

Final Exam First semester Date: 28 /0 1 /20 20

Section 1

Weighting 40 % of the module total

Lecturer: Dr. Qadri Hamarsheh

Coordinator: Dr. Qadri Hamarsheh

Internal Examiner: Eng. Anis Nazer

Marking Scheme

Logic Circuits ( 630211 )

The presented exam questions are organized to overcome course material through 6 questions.

The all questions are compulsory requested to be answered.

Marking Assignments

Question 1 This question is attributed with 10 marks if answered properly; the answers are the following:

Identify the choice that best completes the statement or answers the question.

  1. The binary number 101110101111010 can be written in octal as ________.

a) 51562

8

b) 56577

8

c) 56572

8

d) 65627

8

  1. The excess- 3 code of decimal number 26 is:

a) 01001101 b) 01001001

c) 10001001 d) 01011001

  1. In the circuit shown below, which logic function does this circuit generate?

a) OR b) AND

c) NOR d) NAND

  1. The dual of the Boolean function ๐’™ + ๐’š๐’› is:

a) ๐’™(๐’š + ๐’›)

b) ๐’™(๐’š + ๐’›)

c) ๐’™ + ๐’š๐’›

d) ๐’™ + ๐’š ๐’›

  1. Applying DeMorgan's theorem to the expression

, we get ________

a) b)

c) d)

  1. The K-map for a Boolean function is shown in the figure. The number of essential prime

implicants for this function is

  1. Any combinational circuit can be built using

1. NAND gates. 2. NOR gates. 3. EX-OR gates. 4. Multiplexers.

Which of these are correct?

a) 1, 2 and 3 b) 1, 3 and 4

c) 2, 3 and 4 d) 1,2 and 4

  1. Refer to the following figure, If S

1

=1 and S

2

= 0 what will be the logic state at the output X?

a) X = A b) X = B

c) X = C d) X = D

  1. PRESET and CLEAR inputs are normally synchronous.

a) True b) False

  1. When designing the circuit with the state table shown below using JK flip flops, then J

A

=..., K

A

a) 4 b) 5

c) 6 d) 8

CD

1 1

0 0

0

0 1

00 01 11 10

1 0

1 0

0 0

0 1

00

01

11

10

1

AB

a) (2.5 marks)

Solution

Truth table of half adder is as shown:

b) (2 marks)

Solution

CLK

S

R

Q

Q

time

c) (2.5 marks)

Solution

Question 5 This question is attributed with 5 marks if answered properly; the answers are the following:

Solution

Question 6 This question is attributed with 6 marks if answered properly; the answers are the following:

Solution