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Digital Logic Design and Programming
Typology: Exams
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Logic Circuits (630211)
Final Exam First semester Date: 03/02/
Section 1
Weighting 40% of the module total
Lecturer: Dr. Qadri Hamarsheh
Coordinator: Dr. Qadri Hamarsheh
Internal Examiner: Dr. Naser Halasa
Marking Scheme Logic Circuits (630211)
The presented exam questions are organized to overcome course material through 6 questions. The all questions are compulsory requested to be answered. Marking Assignments
Question 1 This question is attributed with 10 marks if answered properly; the answers are the following:
Which of the following is not a weighted value positional numbering system:
Convert 5278 to binary. a) 011100111 b) 101010111 c) 111010101 d) 343
The Gray code of the binary number 0101 is a) 1111 b) 1000 c) 0111 d) None of the above
Simplification of the Boolean expression ๐จ๐ฉ + ๐จ๐ฉ๐ช + ๐จ๐ฉ๐ช๐ซ + ๐จ๐ฉ๐ช๐ซ๐ฌ + ๐จ๐ฉ๐ช๐ซ๐ฌ๐ญ yields which of the following results? a) (^) ๐๐ b) (^) ๐๐ + ๐๐ + ๐๐ c) (^) ๐จ๐ฉ๐ช๐ซ๐ฌ๐ญ d) (^) ๐ + ๐ + ๐ + ๐ + ๐ + ๐
a) (^) f ๏ฝ A ๏ซ B ๏ซ C ๏ซ E ๏ซ D b) f ๏ฝ A B C ๏ซ E D
c) (^) f ๏ฝ A B C ๏ซ ( E ๏ซ D ) d) f ๏ฝ A ๏ซ B ๏ซ C ๏ซ E D
a) b) c) d) 7 ) The logic function implemented by the circuit below is (ground implies a logic โ0โ)
a) (^) ๐ญ = ๐จ๐ต๐ซ (๐ท, ๐ธ) b) (^) ๐ญ = ๐ถ๐น (๐ท, ๐ธ) c) ๐ญ = ๐ฟ๐ถ๐น (๐ท, ๐ธ) d) ๐ญ = ๐ฟ๐ต๐ถ๐น (๐ท, ๐ธ)
a) hexadecimal b) binary c) binary-coded decimal d) octal
Question 3 This question is attributed with 4 marks if answered properly; the answers are the following: Implement full adder circuit using 4:1 multiplexers.
Question 4 This question is attributed with 7 marks if answered properly; the answers are the following: a) Derive the Boolean equations for D and ๐ต๐๐ข๐ก. (3 marks) Solution
b) Implement D and ๐ต๐๐ข๐ก logic circuits. (2 marks) Solution
P __^ P Q __^ Q Bin B __ in
D
Bout
c) Design the 1-bit full subtractor using 3x8 decoder. (2 marks) Solution
Bin
Q
0
1
2
D E C O D E R
P
3x
D
Bout
Question 5 This question is attributed with 6 marks if answered properly; the answers are the following:
Solution
The flip flop input equations are
The output equations are
D flip flops Thus
State table
State diagram
Question 6 This question is attributed with 7 marks if answered properly; the answers are the following:
