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Digital Logic Lab
Manual
B.Tech.
Computer Science & Engineering
II semester
2009-10(winter)
School of Electrical Sciences
VIT
U N I V E R S I T Y
(Estd. u/s 3 of UGC Act 1956)
Vellore - 632 014, Tamil Nadu, India
The Laboratory Notebook:
Each student must have their own laboratory notebook. All pre-lab exercises and
laboratory reports are to be entered into your notebook.
Students are requested to study the basics before coming to the lab.
Your notebook must be clearly labelled on the cover with the following information:
Course Name : Digital Logic Laboratory
Name :
Register no :
Slot/Batch timing :
Lab faculty Name :
Theory Faculty Name :
- Multiplexer
and
Demultiplexer
- Shift
Registers
- Decade
Counter
- Ring counter
- 4- Bit Binary
Counter
1. VERIFICATION OF LOGIC GATES
AIM:
To study and verify the truth table of logic gates.
TOOL REQUIRED:
Visual SPICE
THEORY:
The logic gates belonging to the TTL family perform the following functions:
OR GATE
If A and B are the inputs then the output Y is given by
Y=A+B, ‘+’ denotes OR operation.
AND GATE
If A and B are the inputs then the output Y is given by
Y=A.B, ‘.’ denotes AND operation.
NOT GATE
If A is the input then the output Y is given by
Y=A’, where ’denotes NOT operation.
The logic gates OR, AND, NOT are called universal gates
NOR GATE
It is NOT operation of the OR logic. If A and B are the inputs then the
output Y is given by
Y= (A+B)’, where ‘+’ denotes OR operation.
NAND GATE
It is NOT operation of the AND logic. If A and B are the inputs then the
output Y is given by
Y= (A.B)’ , ‘.’ denotes AND operation.
TRUTH TABLE:
OR GATE: AND GATE
A B Y=A.B
A B Y=A+B
R=330 Ohms LED
H
L
A
H
L
B
IC 74LS
R=330 Ohms LED
H
L
A
H
L
B
IC 74LS
R=330 Ohms LED
H
L
A
H
L
B
IC 74LS
Y=(AB)
Y=AB' +A'B
Y=(A+B)
NOT GATE NAND GATE
A A’
NOR GATE: EXOR GATE:
PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT:
A B Y=(A.B)’
A B Y=AB’+A’B
A B Y=(A+B)’
Pre Lab Work: (10)
Output Verification: (10)
Viva / Alternate Design: (10)
Total: (30)
LOGIC DIAGRAM : (COMMUTATIVE LAW)
TRUTH TABLE :
INPUT OUTPUT
A B A+B B+A
INPUT OUTPUT
A B A.B B.A
LOGIC DIAGRAM : (ASSOCIATIVE LAW)
TRUTH TABLE
INPUT OUTPUT
A B C A+(B+C) (A+B)+C
INPUT OUTPUT
A B C A.(B.C) (A.B).C
LOGIC DIAGRAM : (IDENTITY LAW)
TRUTH TABLE:
LOGIC DIAGRAM: (REDUNDANCE LAW)
TRUTH TABLE
I/P O/P
A A+A
I/P O/P
A A. A
INPUT OUTPUT
A B A.(A+B)
INPUT OUTPUT
A B A+A.B
PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT:
Pre Lab Work: (10)
Output Verification: (10)
Viva / Alternate Design: (10)
Total: (30)
LOGIC DIAGRAM:
TRUTH TABLE :
INPUT OUTPUT
A B C (A+B+C)’ A’. B’.C’
LOGIC DIAGRAM:
TRUTH TABLE :
INPUT OUTPUT
A B C (A+B+C)’ A’. B’.C’
4.HALF-ADDER AND FULL-ADDER
AIM:
To design and construct a half adder and full adder circuits and verify their
operations.
TOOL REQUIRED:
Visual SPICE
THEORY:
COMBINATIONAL CIRCUITS
Combinational circuits are those circuits which have a number of inputs and may
have one or more than one output. The output at any time depends only upon the inputs at
the very time and is independent of the input values which might have been inputted
earlier. It has no memory element.
HALF ADDER
A half adder is a logic circuit that adds two binary bits. the input to the circuit are
two bits say A and B and output of the circuit are carry and sum, denoted by say C and S.
The Boolean expression for the half adder having the truth table as shown can be
written using karnaugh map for S and C
S=A.B + A.B= A + B
C=A. B
FULL ADDER
When we have to add more than two binary digits we cannot use a number
of half adders as a half adder has on input which can handle carries from other digit.
Hence we need a circuit which takes the bits of the augend, addend and carry, adds them,
and represents the sum and carry, and such a circuit is called full adder.
The Boolean expression for the full adder having the truth table as shown
can be written using k-map for S and C
S=A.B.Cin + A.B.Cin + A.B.Cin + A.B. Cin
= A + B + Cin
C=A.B + B.Cin + A.Cin
LOGIC DIAGRAM : (HALF ADDER)
TRUTH TABLE :( HALF ADDER)
INPUT OUTPUT
A B SUM CARRY
IC 74LS
IC 74LS
L H A L H B
R1=330 Ohms
R2=330 Ohms
LED
LED
SUM=AB'+A'B
CARRY=AB
IC 74LS86 ---> 2-INPUT X-OR GATE IC 74LS08 ----> 2-INPUT AND GATE
HALF ADDER USING LOGIC GATES
