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UC Berkeley EECS Department Exam: RLC Circuits and Digital Circuits, Exams of Electrical Engineering

Punjab Engineering CollegeElectrical Engineering

Information about an exam conducted by the eecs department at uc berkeley. The exam covers topics related to rlc circuits and digital circuits. It includes multiple-choice problems with points assigned to each question. Students are required to show derivations for partial credit and write results into boxes. No electronic devices are allowed during the exam.

Typology: Exams

2012/2013

Uploaded on 04/01/2013

antara
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UC Berkeley, EECS Department B. Boser
EECS 40 MT2: RLC and Digital Circuits UID:
Name:
SID:
UID:
Problem 1 Points of 25
Problem 2 Points of 25
Problem 3 Points of 25
Problem 4 Points of 25
Score %
•Closed book, closed notes
•One pocket calculator permitted (no PDAs, laptops, cell phones, or other electronic devices)
•Show derivations to get partial credit in case of numerical errors
•Cross out incorrect attempts (no partial credit for ambiguous derivations)
•Write results into boxes
•Take off hats or caps and leave backpacks and electronic devices in isle
Password:
1April 15, 2009 MT2 v1142
pf3
pf4
pf5

Partial preview of the text

Download UC Berkeley EECS Department Exam: RLC Circuits and Digital Circuits and more Exams Electrical Engineering in PDF only on Docsity!

UC Berkeley, EECS Department B. Boser

EECS 40 MT2: RLC and Digital Circuits UID:

Name:

SID:

UID:

Problem 1 Points of 25

Problem 2 Points of 25

Problem 3 Points of 25

Problem 4 Points of 25

Score %

  • Closed book, closed notes
  • One pocket calculator permitted (no PDAs, laptops, cell phones, or other electronic devices)
  • Show derivations to get partial credit in case of numerical errors
  • Cross out incorrect attempts (no partial credit for ambiguous derivations)
  • Write results into boxes
  • Take off hats or caps and leave backpacks and electronic devices in isle

Password:

  1. Capacitor C 1 in the circuit below is discharged at t = 0. Use V 1 = V, R 1 = kΩ and C 1 = nF. Calculate

a) the energy stored on the capacitor at time t = 0. 5 pts. 0 b) the energy stored on the capacitor at time t → ∞. 5 pts. 1 c) the total energy delivered by the source V 1 for t = 0... ∞. 15 pts. 2

  1. The circuit below is a partial implementation of a logic gate that computes the output Y from inputs A, B, and C. a) (15 points) Add transistors as needed to complete the implementation such that for all binary input combi- nation the output is either connected to Vdd or ground but not both. b) (10 points) Fill out the truth table of the logic gate for all possible inputs.

A B C Y

  1. In the circuit below switch S 1 is open for t < 0 and the current through L 1 = mH is zero. At time t = 0 the switch closes, and reopens at time t = T 1. Calculate T 1 such that the voltage across R 1 = Ω just after the switch reopens is vR(t = T 1 ) = V. Use V 1 = V.

T 1 =

25 pts. 5