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The guidelines, problem statement, and scoring information for the midterm ii exam of the eecs 40 course at the university of california, berkeley, department of electrical engineering and computer sciences, held in spring 1999. The exam covers topics related to micromirror structures, integrated circuit resistor structures, and switched capacitor circuits.
Typology: Exams
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University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences
Spring 1999 Prof. Roger T. Howe April 14, 1999
_Name: ______________________ Student ID ______________ last, first
Guidelines
Score
Problem
Points Possible Score
Poly1 Mask (clear field)
Oxide1 Mask (clear field)
Oxide2 Mask (dark field)
Metal Mask (clear field)
y , [μm]
x , [μm]
Poly2 Mask (clear field)
(c) [3 pts.] Find the numerical value of the capacitance between terminals 1 and 2 in femtoFarads (fF). Use the layout on p. 2 to estimate the area of the capacitor. Note that the substrate is grounded, so it has no contribution to the answer to this part. Hint: terminal 1 is connected to a poly2 structure, whereas terminal 2 is connected to a poly1 structure. The capacitance is between the two polysilicon structures.
(d) [3 pts.] Find the numerical value of the capacitance between terminal 3 and the substrate. Neglect the contribution from the metal layer. Hint: you are not expected to consider capacitors in series to find the answer.
A A’
V (^0) -
V (^2) -
V (^3) -
I 0
I 2 I^3
I 1
c
b
a
V 0 V 1 V 2 V 3 SiO 2
Doping concentrations and thicknesses of regions a , b , and c :
a 3 x 10^17 cm-3^ boron, 2.5 x 10^17 cm-3^ phosphorus (0.5 μm thick) b 1017 cm-3^ boron, 2.5 x 10^17 cm-3^ phosphorus (1 μm thick) c 1017 cm-3^ boron (substrate)
80 μm (^5) μm
Given Electron mobility: (^) μ n = 1000 cm^2 /(Vs) Hole mobility: (^) μ p = 400 cm^2 /(Vs) Unit charge: q = 1.6 x 10-19^ C
1 μm^ 0.5^ μm
(a) [2 pts.] What is the type (n or p) and the sheet resistance of layer a in the IC structure whose layout and cross section is shown in the figure?
Switch operation
t (μs)
HINT: This problem is MUCH SIMPLER than it looks!
(a) [3 pts.] Find the charge stored on each capacitor at the time t = 0.5 μs, given that C = 50 fF and Vin = 1 V. Hint: draw the circuit at that time, using the switch states given above.
(b) [3 pts.] Find the charge stored on each capacitor at the time t = 1.5 μs, given that C = 50 fF and Vin = 1 V. The same hint from part (a) applies.
(c) [4 pts.] Find the output voltage Vout at the time t = 1.5 μs, given that C = 50 fF and Vin = 1 V. The same hint from part (a) applies.