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University of California, Berkeley College of Engineering Computer Science Division EECS Fall 2010 John Kubiatowicz
Midterm I
October 18th, 2010 CS162: Operating Systems and Systems Programming
Your Name:
SID Number: Circle the letters of CS Login
First: a b c d e f g h I j k l m n o p q r s t u v w x y z Second: a b c d e f g h I j k l m n o p q r s t u v w x y z
Discussion Section:
General Information: This is a closed book exam. You are allowed 2 pages of notes (both sides). You may use a calculator. You have 3 hours to complete as much of the exam as possible. Make sure to read all of the questions first, as some of the questions are substantially more time consuming.
Write all of your answers directly on this paper. Make your answers as concise as possible. On programming questions, we will be looking for performance as well as correctness, so think through your answers carefully. If there is something about the questions that you believe is open to interpretation, please ask us about it!
Problem Possible Score
Total 100
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Problem 1f[2pts]: “ Hyperthreading” is a term used to describe systems with thousands of threads.
True / False
Explain:
Problem 1g[2pts]: A Lottery Scheduler can be used to implement any other scheduling algorithm by adjusting the number of tickets that each process holds.
True / False
Explain:
Problem 1h[2pts]: A MicroKernel can improve the resilience of a system against bugs in the OS.
True / False
Explain:
Problem 2: Short Answer [22pts] Problem 2a[2pts]: What is priority donation and why is it important?
Problem 2b[3pts]: Name three ways in which the processor can transition from user mode to kernel mode. Can the user execute arbitrary code after transitioning?
Problem 2c[2pts]: What happens when an interrupt occurs? What does the interrupt controller do?
Problem 2d[2pts]: Explain how to fool the multi-level feedback scheduler’s heuristics into giving a long-running task more CPU cycles.
Problem 2i[4pts]: Here is a table of processes and their associated arrival and running times.
Process ID Arrival Time CPU Running Time Process 1 0 2 Process 2 1 6 Process 3 4 1 Process 4 7 4 Process 5 8 3
Show the scheduling order for these processes under 3 policies: First Come First Serve (FCFS), Shortest-Remaining-Time-First (SRTF), Round-Robin (RR) with timeslice quantum = 1. Assume that context switch overhead is 0 and that new processes are added to the head of the queue except for FCFS, where they are added to the tail.
Time Slot FCFS SRTF RR
0 1 2 3 4 5 6 7 8 9
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Assume that our system uses Mesa scheduling and that condition variables have FIFO wait queues. Below is a sketch of a solution that uses only two condition variables and that does return results as if requests were processed in logical arrival order. Rather than separate methods for Reader() and Writer(), we have a single method which takes a “NewType” variable (0 for read, 1 for write):
- Lock MonitorLock; // Methods: acquire(),release()
- Condition waitQueue, onDeckQueue;// Methods: wait(),signal(),broadcast()
- int Queued = 0, onDeck = 0; // Counts of sleeping threads
- / Missing code /
- Accessor (int NewType) { // type = 0 for read, 1 for write
- /* Monitor to control entry so that one writer or multiple readers */
- MonitorLock.acquire();
- / Missing wait condition /
- { Queued++;
- waitQueue.wait();
- Queued—;
- }
- / Missing wait condition /
- { onDeck++;
- onDeckQueue.wait();
- onDeck--;
- }
- / Missing code /
- MonitorLock.release();
- // Perform actual data access
- AccessDatabase(NewType);
- / Missing code /
- }
The waitQueue condition variable keeps unexamined requests in FIFO order. The onDeckQueue keeps a single request that is currently incompatible with requests that are executing. W e want to allow as many parallel requests to the database as possible, subject to the constraint of obeying logical arrival order. Here, logical arrival order is defined by the order in which requests acquire the lock at line #7.
Problem 3c[2pts]: What additional variable(s) (and initialization) do you need at Line #4? Hint: think about what you need to describe the current set of threads accessing the database in parallel. Give explicit code to insert at Line #4 (can be more than one line of actual code).
Problem 3d[2pts]: Explain why you might not want to use a “while()” statement in Line #8 – despite the fact that the system has Mesa scheduling :
Problem 3e[2pts]: What is the missing code in Line #8? Hint: it is a single “if” statement.
Problem 3f[2pts]: What is the missing code in Line #13? This should be a single line of code.
Problem 3g[2pts]: What is the missing code in Line #18? You should not have more than three (3) actual lines of code.
Problem 3h[3pts]: What is the missing code in Line #22? You should not have more than five (5) actual lines of code.
Problem 3i[3pts]: Suppose that condition variables did not have FIFO ordered wait queues. What changes would you have to make to your code? Be explicit (you should not need more than 6 new or changed lines). Hint: consider assigning a sequentially increasing ID to each thread.
Problem 4: Deadlock [24pts] Problem 4a[2pts]: Suppose that we utilize the Banker’s algorithm to determine whether or not to grant resource requests to threads. The job of the Banker’s algorithm is to keep the system in a “SAFE” state. It denies resource requests by putting the requesting thread to sleep if granting the request would cause the system to enter an “UNSAFE” state, waking it only when the request could be granted safely. What is a SAFE state?
Problem 4b[4pts]: The figure at the right illustrates a 2D mesh of network routers. Each router is connected to each of its neighbors by two network links (small arrows), one in each direction. Messages are routed from a source router to a destination router and can stretch through the network (i.e. consume links along the route from source to destination). Messages can cross inside routers. Assume that no network link can service more than one message at a time, and that each message must consume a continuous set of channels (like a snake). Messages always make progress to the destination and never wrap back on themselves. The figure shows two messages (thick arrows). Assume that each router or link has a very small amount of buffer space and that each message can be arbitrarily long. Show a simple situation (with a drawing) in which messages are deadlocked and can make no further progress. Explain how each of the four conditions of deadlock are satisfied by your example. Hint: Links are the limited resources in this example.
R R R R
R R R R
R R R R
R R R R
R R R R
R R R R
R R R R
R R R R
RRR RRR RRR RRR
RRRR RRRR RRRR RRRR
RRRR RRRR RRRR RRRR
RRRR RRRR RRRR RRRR
Problem 4c[3pts]: Define a routing policy that avoids deadlocks in the network of (4b). Prove that deadlocks cannot happen when using this routing policy. Hint: assume that a deadlock occurs and show why that leads to a contradiction in the presence of your new routing policy.
Problem 4d[3pts]: Suppose that we wanted a less restrictive routing policy than your answer to (4c). Explain why the Banker’s algorithm is not well adapted to this routing problem. What could you do that was similar in spirit to the Banker’s algorithm to prevent deadlock in networks such as (4b), while allowing arbitrary routing of messages? Why is it unlikely that such an algorithm would be used in a real network?
Problem 4e[2pts]: Is it possible for a system with a single monitor (i.e one lock with multiple condition variables) to deadlock? Explain.
Problem 4g[3pts]: Assume that we start with a system in the state of (4f). Suppose that T1 asks for 2 more copies of resource A. Can the system grant this if it wants to avoid deadlock (i.e. will the result be a SAFE state)? Explain.
Problem 4h[3pts]: Assume that we start with a system in the state of (4f). What is the maximum number of additional copies of resources (A, B, and C) that T1 can be granted in a single request without risking deadlock? Explain.
Problem 5: Virtual Memory [18pts] Consider a two-level memory management scheme on 24-bit virtual addresses using the following format for virtual addresses:
Virtual Page # (8 bits)
Virtual Page # (8 bits)
Offset (8 bits)
Virtual addresses are translated into 16-bit physical addresses of the following form:
Physical Page # (8 bits)
Offset (8 bits)
Page table entries are 16 bits in the following format, stored in big-endian form in memory (i.e. the MSB is first byte in memory).
Page Table Entry (PTE)
Physical Page # (8 bits)
Kernel OnlyUncacheable
0 0
DirtyUse WriteValid
Note that a virtual-physical translation can fail at any point if an incompatible PTE is encountered. Two types of errors can occur during translation: “invalid page” (page is not mapped at all) or “access violation” (page exists, but access was illegal).
Problem 5a[2pts]: How big is a page? Explain.
Problem 5b[2pts]: What is the largest size for a page table with this address space? We are asking for the total size of both levels of the page table. Explain.
Problem 5c[3pts]: What does “TLB” stand for and what is its function? How big would a TLB entry be for this system?
Virtual Address Format
Virtual Page # (8 bits)
Virtual Page # (8 bits)
Offset (8 bits)
Page Table Entry (PTE)
Physical Page # (8 bits)
Kernel Not
Cacheable 0 0
DirtyUse WriteValid
Physical Memory
Address +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
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