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Question 1. Which of the following best describes the primary design goal of an embedded system? A) Maximizing user interface complexity B) Optimizing under constraints such as power, cost, and real‑time performance C) Achieving the highest possible clock frequency D) Supporting a wide variety of operating systems Answer: B Explanation: Embedded design focuses on meeting functional requirements while staying within strict limits on power consumption, cost, and timing. Question 2. A cyber‑physical system is characterized by which combination? A) Pure software execution on a desktop CPU B) Interaction between computational elements and physical processes C) Use of only wireless communication protocols D) Absence of any real‑time constraints Answer: B Explanation: Cyber‑physical systems tightly couple computation with physical dynamics (sensors/actuators). Question 3. In the N‑way trade‑off for embedded design, which factor is NOT typically considered? A) Power consumption B) Performance C) Unit cost D) Color of the PCB Answer: D
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Explanation: Power, performance, cost, and time‑to‑market are the classic trade‑offs; PCB color is irrelevant. Question 4. Which phase of the embedded design process involves translating user requirements into formal specifications? A) Architecture design B) Requirements engineering C) System integration D) Verification and validation Answer: B Explanation: Requirements engineering gathers and formalizes what the system must do. Question 5. In ARM architecture, which register holds condition flags such as Zero and Carry? A) R B) SP (Stack Pointer) C) CPSR (Current Program Status Register) D) LR (Link Register) Answer: C Explanation: CPSR contains condition flags, mode bits, and interrupt status. Question 6. The ARM load/store architecture means that: A) All arithmetic instructions can directly access memory B) Only load and store instructions access memory, all others operate on registers C) Memory is accessed via a special address register only D) Instructions are variable‑length depending on memory access
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D. External I/O drivers Answer: B Explanation: Static power arises from sub‑threshold and gate‑oxide leakage when the circuit is idle. Question 10. The dynamic power equation P = α C V² f shows that power is proportional to which of the following? A. Square of the supply voltage and linearly with frequency B. Linear with voltage and quadratic with frequency C. Quadratic with capacitance and inversely with frequency D. Independent of activity factor α Answer: A Explanation: Dynamic power grows linearly with frequency and quadratically with voltage; α is the activity factor. Question 11. SRAM differs from DRAM primarily because: A. SRAM requires periodic refresh cycles B. SRAM stores data using capacitors C. SRAM is faster and does not need refresh, but is less dense and more expensive D. SRAM can only be used as cache memory Answer: C Explanation: SRAM uses bistable latches, giving speed and no refresh, at higher area cost. Question 12. Which cache mapping scheme offers the highest flexibility in placement of memory blocks? A. Direct‑mapped cache
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B. Set‑associative cache C. Fully associative cache D. Victim cache Answer: C Explanation: Fully associative caches allow any block to be placed in any line, maximizing flexibility. Question 13. In a set‑associative cache with 4‑way associativity, how many lines can a given memory block map to? A. 1 B. 2 C. 4 D. All lines in the cache Answer: C Explanation: 4‑way set‑associative means each set contains 4 lines; a block can be placed in any of those 4. Question 14. The primary function of a Memory Management Unit (MMU) is to: A. Increase cache hit rate by prefetching data B. Translate virtual addresses to physical addresses and enforce protection C. Perform error‑correcting code (ECC) on DRAM D. Provide DMA channels for peripheral devices Answer: B Explanation: MMU handles address translation and access rights. Question 15. Direct Memory Access (DMA) improves system throughput by:
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A. MOSI and MISO B. SDA (data) and SCL (clock) C. TX and RX D. CS and SCK Answer: B Explanation: I²C is a two‑wire serial bus with a data line (SDA) and a clock line (SCL). Question 19. Which protocol is full‑duplex and typically operates at higher speeds than I²C? A. UART B. SPI C. CAN D. LIN Answer: B Explanation: SPI provides simultaneous send/receive on separate lines and can run at tens of MHz. Question 20. In asynchronous serial communication (UART), what determines the bit timing? A. An external clock line provided by the master B. A shared PLL between transmitter and receiver C. Pre‑agreed baud rate configured in both devices D. The length of the data packet Answer: C Explanation: UART devices must be set to the same baud rate; timing is derived locally.
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Question 21. A task in an RTOS that is currently not executing because it is waiting for a resource is in which state? A. Running B. Ready C. Blocked D. Suspended Answer: C Explanation: Blocked (or waiting) tasks cannot run until the awaited condition occurs. Question 22. Context switching in an RTOS typically requires saving which of the following? A. Only the program counter (PC) B. The PC, stack pointer, and processor registers C. Only the status flags in CPSR D. The contents of the data cache Answer: B Explanation: Full context includes PC, SP, general‑purpose registers, and status registers. Question 23. Rate Monotonic Scheduling (RMS) assigns priorities based on: A. Shorter deadlines → higher priority B. Longer periods → higher priority C. Shorter periods → higher priority (static) D. Random assignment at runtime Answer: C Explanation: RMS is a static priority scheme where tasks with shorter periods get higher priority.
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Explanation: The medium‑priority task prevents the low‑priority holder from releasing the resource, effectively inverting priorities. Question 27. Which IPC mechanism provides deterministic communication latency suitable for hard‑real‑time systems? A. Message queues with variable length B. Shared memory with mutex protection C. Pipes with kernel buffering D. Signals generated by the OS Answer: B Explanation: Shared memory enables direct data transfer without kernel mediation, offering predictable latency when protected properly. Question 28. In the compilation flow, which stage translates high‑level language constructs into assembly language? A. Pre‑processor B. Compiler C. Assembler D. Linker Answer: B Explanation: The compiler parses source code and generates assembly (or intermediate code) before assembly. Question 29. Loop unrolling primarily reduces which type of overhead? A. Memory bandwidth usage B. Branch instruction overhead caused by loop control
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C. Register pressure D. Cache miss rate Answer: B Explanation: By replicating the loop body, fewer branch instructions are executed, reducing control overhead. Question 30. Register allocation aims to: A. Increase the number of global variables B. Minimize memory accesses by keeping frequently used variables in registers C. Reduce the size of the instruction cache D. Allocate more stack space for function calls Answer: B Explanation: Keeping variables in registers reduces load/store operations, improving speed. Question 31. Worst‑Case Execution Time (WCET) analysis is essential for: A. Estimating average power consumption B. Ensuring that real‑time tasks meet their deadlines under worst‑case conditions C. Minimizing code size D. Determining cache hit ratios Answer: B Explanation: WCET provides an upper bound on execution time, crucial for deadline guarantees. Question 32. In hardware/software co‑design, partitioning refers to: A. Dividing the PCB into separate layers B. Deciding which functions will be implemented in hardware (e.g., FPGA) and which in software
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B. It determines the maximum operating temperature of the device C. It dictates the choice of instruction set architecture D. It controls the power supply design Answer: A Explanation: Reducing development cycles can give a competitive advantage and increase profitability. Question 36. In a real‑time system, “hard” deadlines mean: A. Missing the deadline occasionally is acceptable B. The deadline must be met under all circumstances; failure leads to system failure C. Deadlines are only advisory for best‑effort scheduling D. The deadline can be extended dynamically by the scheduler Answer: B Explanation: Hard real‑time constraints require absolute adherence; missing them can cause catastrophic outcomes. Question 37. Which bus protocol supports multi‑master operation and is commonly used for sensor interfacing? A. SPI B. I²C C. UART D. CAN Answer: B Explanation: I²C allows multiple masters to control the bus, making it suitable for sensor networks.
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Question 38. The primary advantage of a fully associative cache over a direct‑mapped cache is: A. Simpler hardware implementation B. Elimination of cache conflicts (higher hit rate) C. Lower power consumption D. Smaller tag storage requirements Answer: B Explanation: Fully associative caches can place any block in any line, reducing conflict misses. Question 39. Which of the following best describes a “time‑critical” execution requirement? A. The code must finish within a known, bounded time interval B. The code should be as fast as possible, regardless of deadlines C. The code can be executed at any time as long as it is correct D. The code must use the maximum possible CPU frequency Answer: A Explanation: Time‑critical tasks have strict timing constraints that must be guaranteed. Question 40. In a set‑associative cache, the “way” refers to: A. The number of bits used for the tag field B. The number of lines in each set C. The size of the cache line in bytes D. The total number of sets in the cache Answer: B Explanation: “Way” denotes the number of lines (or “ways”) per set.
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Explanation: Many RTOSes avoid complex virtual memory to keep deterministic behavior. Question 44. The “priority inversion” problem can be mitigated by which protocol? A. Round‑Robin scheduling B. Priority inheritance C. FIFO queuing D. Token bucket shaping Answer: B Explanation: Priority inheritance temporarily raises the priority of the low‑priority task holding the resource. Question 45. In the context of embedded flash memory, “wear‑leveling” is used to: A. Increase read speed by caching frequently accessed sectors B. Evenly distribute erase/write cycles across the memory to prolong its life C. Reduce power consumption during idle periods D. Encrypt data stored in flash cells Answer: B Explanation: Wear‑leveling balances usage to avoid premature failure of particular blocks. Question 46. Which of the following best describes “pre‑emptive” scheduling? A. A task runs to completion before another can start B. The scheduler can interrupt a running task to start a higher‑priority task C. Tasks are scheduled based on round‑robin time slices only D. The scheduler only runs when the system is idle Answer: B
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Explanation: Pre‑emptive scheduling allows the OS to suspend lower‑priority tasks for higher‑priority ones. Question 47. A “soft‑real‑time” system differs from a hard‑real‑time system in that: A. It has no timing constraints at all B. Missing a deadline degrades performance but does not cause catastrophic failure C. It must meet deadlines with 100 % certainty D. It uses non‑deterministic scheduling algorithms exclusively Answer: B Explanation: Soft‑real‑time tolerates occasional deadline misses, affecting quality but not safety. Question 48. In the compiler optimization technique of “strength reduction,” an expensive operation is replaced by: A. A more complex algorithm B. A cheaper operation such as addition or shift C. A hardware accelerator call D. A recursive function Answer: B Explanation: Strength reduction swaps costly multiplications/divisions with cheaper additions/shifts. Question 49. Which of the following hardware structures is essential for supporting context switching in an RTOS? A. A dedicated stack pointer register per task B. An on‑chip GPU C. A large L2 cache
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C. External sensor interface D. Clock generator (PLL) Answer: A Explanation: The CPU can enter low‑power sleep states; other peripherals may stay powered if needed. Question 53. The term “latency” in interrupt‑driven I/O most directly refers to: A. The time between peripheral event occurrence and start of ISR execution B. The total time the CPU spends in the ISR C. The bandwidth of the data transfer D. The clock frequency of the bus Answer: A Explanation: Interrupt latency is the delay from event to ISR entry. Question 54. Which scheduling algorithm guarantees optimal processor utilization for a set of independent, preemptable, periodic tasks on a uniprocessor? A. Rate Monotonic Scheduling (RMS) B. Earliest Deadline First (EDF) C. Round‑Robin D. FIFO Answer: B Explanation: EDF is optimal; if a feasible schedule exists, EDF will find it. Question 55. In a microcontroller, the “watchdog timer” is used to: A. Generate periodic interrupts for task scheduling
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B. Reset the system if software becomes unresponsive, improving reliability C. Measure execution time of functions D. Provide a high‑resolution clock for timestamps Answer: B Explanation: The watchdog forces a reset when not periodically cleared, protecting against hangs. Question 56. Which of the following best describes “static power” in CMOS circuits? A. Power consumed only when the circuit is actively switching B. Power due to leakage currents when transistors are idle C. Power proportional to the square of the supply voltage D. Power generated by the oscillator circuit Answer: B Explanation: Static power arises from sub‑threshold and gate leakage independent of switching activity. Question 57. In the context of embedded flash, what does “program/erase cycle” refer to? A. The process of reading data from flash memory B. The act of writing (programming) and subsequently erasing a flash block, which degrades the cell over time C. The clock cycle required to access flash D. The security authentication before flash access Answer: B Explanation: Each program/erase operation stresses the floating‑gate, limiting endurance.
