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Week 2: Addressing Modes (^1)
Machine Code
The commands the CPU understands
Machine Code
A set of binary codes that are
recognised and executed directly
by a particular CPU
Week 2: Addressing Modes (^3)
Machine Instructions
• An individual machine code is called a
Machine Instruction
- e.g. the machine instruction to add 1 to the
value in accumulator A is 01001100
• The set of all codes recognized by a
particular CPU is known as its Instruction
Set
Machine Instructions
• A typical machine instruction consists of an
operation code (op-code), which specifies
what operation the CPU is to do, plus a
number of arguments, which specify what
data the CPU is to operate on
- e.g. the machine instruction to add 2 to the
value in accumulator A is 10001011 00000010
Week 2: Addressing Modes (^5)
What Do/Can Machine Instructions Do?
• We can group the instructions according to
function. The groups given here are
generally applicable to most instruction sets
(i.e. they apply to the machine code for
most types of processor)
Instructions: Data Transfer
• From where, to where?
• load (e.g. from memory to a register)
• store (e.g. from a register to memory)
• move (e.g. from register to register)
Week 2: Addressing Modes (^7)
Instructions: Computations
• The arithmetic and logical operations,
normally carried out by the ALU
(Arithmetic Logic Unit)
• What might this include?
- add
- subtract
- increment
- invert bits
- … and more
Instructions: Flow Control
• A computer program is not a lot of use
without loops, functions, etc.
• We need to have machine codes to control
the flow of execution through a machine
code program
• Branching, jumping to subroutines,
returning from subroutines
Week 2: Addressing Modes (^13)
68HC11 Architecture: Programmers Model
7 Accumulator A 0 7 Accumulator B 0 15 Double accumulator D 0 15 Index register IX 0 15 Index register IY 0 15 Stack pointer 0 15 Program counter 0 S X H I N Z V C
A:B D IX IY SP PC CCR Condition Code Register Carry Overflow Zero Negative I interrupt mask Half-carry (from bit 3) X interrupt mask Stop disable
Instruction: LDAA immediate
mnemonic: LDAA
op-code: 86 (hex)
operation: Load accumulator A with the
8-bit value immediately
following the op-code
dd
addresses increasing op code for LDAA data to be loaded
Week 2: Addressing Modes (^15)
Instruction: LDAA direct
mnemonic: LDAA
op-code: 96 (hex)
operation: Load accumulator A with the
contents of memory location
given by 8-bit number
following the op-code
dd
addresses increasing op code for LDAA address of data to be loaded
Why two instructions with the
same mnemonic?
- They perform the same operation, but the source is
different
- We say they use different addressing modes
- Customarily, the same mnemonic is used for all
operations that perform essentially the same
operation, and differ only in their addressing modes
- It’s the syntax (in assembly code) which
differentiates them
Week 2: Addressing Modes (^17)
Addressing Modes Example
LDAA immediate to load the value (decimal) 30 into
accumulator A would be written:
LDAA
LDAA direct to load the contents of address 30 into
accumulator A would be written:
LDAA 30
The # sign distinguishes between them
Memory consists of addressable locations. A memory location has 2 components:
Data transfer between CPU and memory involves address bus and data bus
CPU memory
address bus lines
data bus lines
address contents
Memory Addressing
Week 2: Addressing Modes (^19)
Endian-ness
• 68HC11 is a big endian microprocessor.
• When we write a 16 bit in a memory
location, the first byte of memory contains
the high portion of the 16 bit number.
• Big Endian à Big End in First
• Small Endian à Small end in First
• Intel 80x86, Pentium processors are the
examples of Small Endian machines.
Machine Language Execution
How Machine Language Programs
Are Executed on the CPU?
Week 2: Addressing Modes (^25)
LDAA $D
• Step 1: Assume PC=$C000. $C000 is
placed on A-bus and READ issued.
• Step 2: 8-bit content at location $C
($B6 ) is returned on data bus and place in
the Instruction Decode Register (IDR) in the
control unit.
- PC is incremented by 1 to become $C
- The machine instruction loaded into IDR will be
analyzed to understand what to do next in the
control unit.
LDAA $D000 ($B6 $D0 $00)
CPU
IDR
.. $B6 [$C000] $D0 [$C001] $00 [$C002] $BB [$C003] $D0 [$C004] $01 [$C005] $B7 [$C006] $D0 [$C007] $00 [$C008] .. $19 [$D000] $37 [$D001] ..
Step 1: A-bus ($C000-READ)
Step 2: $B6 is returned on D-bus. PC ß $C
Week 2: Addressing Modes (^27)
LDAA $D000 ($B6 $D0 $00)
- Step 3: Control unit (decoder) recognizes LOAD
instruction. This instruction needs 2-byte value for
operand address.
- Issues two READ cycles:
- address bus-READ -$C001 à data bus returns $D
- address bus-READ -$C002 à data bus returns $
- At the end PC becomes $C
- Step 4: Execution of the instruction ($B6) needs
the content of location $D000. A READ is issued
with address = $D000 à data bus returns $19 and
that is put into register A.
CPU
IDR
.. $B6 [$C000] $D0 [$C001] $00 [$C002] $BB [$C003] $D0 [$C004] $01 [$C005] $B7 [$C006] $D0 [$C007] $00 [$C008] .. $19 [$D000] $37 [$D001] ..
Step 3: A-bus ($C001 & $C002 READ)
$D0 & $00 is returned on D-bus saperately and put into Memory Address Register (MAR)
LDAA $D000 ($B6 $D0 $00)
MAR
Week 2: Addressing Modes (^29)
CPU
IDR
.. $B6 [$C000] $D0 [$C001] $00 [$C002] $BB [$C003] $D0 [$C004] $01 [$C005] $B7 [$C006] $D0 [$C007] $00 [$C008] .. $19 [$D000] $37 [$D001] ..
Step 4: A-bus ($D000 - READ)
$19 is returned on D-bus and put into register A (Accumulator A)
MAR
LDAA $D000 ($B6 $D0 $00)
ACCA
ADDA $D001 ($BB $D0 $01)
- Step 1: PC=$C003, $C003 is placed on A-bus and
READ is issued.
- Step 2: 8-bit content at location $C003=$BB is
returned on data bus and place in IDR. PC is
incremented by 1 to become $C004.
- Step 3: Control unit (instruction decoder)
recognizes ADD instruction. Needs a 2-byte value
for operand address and it issues 2 READ cycles:
- address bus = $C004 à data bus = $D
- address bus = $C005 à data bus = $
- At the end, PC becomes $C
MAR
Week 2: Addressing Modes (^31)
ADDA $D001 ($BB $D0 $01)
- Step 4: Execution of the instruction needs the
content of location $D
- A READ is issued with address bus = $D001 and
data bus returns $37 (put into MDR - Memory
Data Register in the control unit).
- Step 5: ALU adds the content of MDR ($37) to
ACCA ($19) so that ACCA becomes $50.
STAA $D001 ($B7 $D0 $01)
- Step 1: PC = $C006, $C006 is placed on address bus and READ is issued.
- Step 2: 8-bit content at location $C006 = $B7 is returned on data bus and placed in IDR. PC is incremented by 1 to become $C007.
- Step 3: Control unit (instruction decoder) recognizes STORE instruction. It needs a 2-byte value for operand address. It issues two separate READ cycles - address bus = $C007 à data bus = $D - address bus = $C008 à data bus = $ - At the end PC becomes $C
- Step 4: Execution of the instruction needs to issue a WRITE to memory with address bus = $D001 and data bus = $
Week 2: Addressing Modes (^37)
68HC11 Immediate
• An 8-bit or 16-bit argument immediately
follows the op-code
LDAA
signifies immediate mode
The argument (specified in decimal, by default)
Direct (or Absolute)
• The address of the argument (8 bit) follows
the op-code
• That is, the number which follows the op-
code is treated as an address at memory
locations [$00 - $FF], and the CPU will
look there for the actual argument.
Week 2: Addressing Modes (^39)
68HC11 Direct
• An 8-bit address in the range 0…
follows the op-code
LDAA 23
LDAA $FF
No # sign, so we know it’s not in immediate mode <256, so it must be direct
$ means it’s hex
FF hex = 255 decimal, so it’s still direct
Extended
• The address of the argument (16 bit)
follows the op-code
• That is, the number which follows the op-
code is treated as an address at memory
locations [$0000 - $FFFF], and the CPU
will look there for the actual argument.
• Using this addressing mode, memory space
of HC11 can be fully accessed.
Week 2: Addressing Modes (^41)
68HC11 Extended
• A full 16-bit address follows the op-code
• LDAA 257
• LDAA $
No #, so we know it’s not immediate >255, so it can’t be direct, and must therefore be extended
$ means it’s hex
255 hex = 597 decimal, so it’s extended
Relative
• The relative address of the argument
follows the op-code
• Relative addresses specify where the
argument is relative to the current value of
the PC
• The CPU calculates the actual address by
adding together the relative address and the
current value of the PC
Week 2: Addressing Modes (^43)
68HC11 Relative
• This is slightly different. It’s only used in
branch instructions – see later in the course
• To recognise a branch instruction, look for
the B. (BRA, BNE, BLS, BGS etc)
BRA $F
BNE $
Jump location at [PC – 8]
Jump $21 bytes ahead [PC+$21]
Indexed
• The address of the argument is the value
currently stored in a specified index register
(or general-purpose register) plus an offset
that immediately follows that op-code
• 68HC11 has two index registers IX and IY
• Useful for implementing arrays!
Week 2: Addressing Modes (^49)
Others (not 68HC11)
- register
- The argument is the current contents of a specific register
- register-indirect
- The address of the argument is the current value of a specified register
- register-autoincrement/decrement
- As register-indirect, but adjust register to point to next/previous location before or after using its value
- Indirect
- The number following the op-code is the address of a memory location that contains the address of the argument
All of LDAA Instructions
ind, Y 18 B6^ dd^ LDAA^ dd , Y
ind, X B6^ dd^ LDAA^ dd , X
ext A6^ dd dd^ LDAA^ dddd
dir^96 dd^ LDAA^ dd
imm^86 dd^ LDAA # dd
Assembly-
code syntax
Mode Machine codes
How can we Differentiate Addressing Modes?
Are These Numbers Chosen Randomly?
Week 2: Addressing Modes (^51)
Patterns in Machine Code
Machine codes are not chosen at random!
LDAB ind, X F6 1 1 1 1 0 1 1 0
LDAB ext E6 1 1 1 0 0 1 1 0
LDAB dir D6 1 1 0 1 0 1 1 0
LDAB imm C6 1 1 0 0 0 1 1 0
LDAA ind, X B6 1 0 1 1 0 1 1 0
LDAA ext A6 1 0 1 0 0 1 1 0
LDAA dir 96 1 0 0 1 0 1 1 0
LDAA imm 86 1 0 0 0 0 1 1 0
defines the addressing mode
How is Addressing Mode Specified?
• In most cases, set by bits from opcode
• ADDA: $8B $9B $BB $AB
• ADDB: $CB $DB $FB $EB
1 A/B AM1 AM0 1 0 1 1
Selects Register A for 0 or B for 1
00 immediate 01 Direct 10 Extended 11 Indexed
code for ADD
Opcode (8bit) format
Week 2: Addressing Modes (^53)
Some Arithmetic Instructions
ADDA add 8-bit word to accumulator A
ADDB add 8-bit word to accumulator B
ADDD add 16-bit word to double accumulator D
ABA add B to A
Equivalent subtraction operations are:
SUBA, SUBB, SUBD, SBA
Other Instructions
There are also instructions to:-
• Increment, decrement or negate a register or
memory location
• Perform bitwise logical operations such as
AND, OR, XOR and NOT
• Perform shifts, rotates, and many more
logical and arithmetic operations
Week 2: Addressing Modes (^55)
Conditionals
Bits in Condition Code Register
Condition Code Register (CCR)
• 5 status bits.
- Certain bits in CCR indicate the situation after
the operation. For instance, if previous
operation yields a zero output, Z flag becomes
one.
• 2 interrupt masking bits (later)
• 1 stop disable bit (later)
Week 2: Addressing Modes (^61)
Example 2
MSB LSB 130
163 1 0 1 0 0 0 1 1
C
Add 130 and 163, and determine if carry bit is set or not.
LDAA # LDAB # ABA
The result is 9 bits, we use C flag as the 9th bit.
Example 3 (16 bit addition)
1 1 0 00 1 0 0 0 1 1 00 0 1 0
MSB LSB 50274
28712
C
LDD # ADDD #
The result is 17 bits (exceeds 65535), we use C flag as the 17th bit.
0 1 1 10 0 0 0 0 0 1 01 0 0 0
1 0 01 1 0 10 0 1 0 00 1 0 1 0
Week 2: Addressing Modes (^63)
Handling of Signed Numbers
• 6811 handles signed numbers using the 2’s
complement numbering system
• Recall the most significant bit is the sign
• You negate a number by taking its 2’s
complement (e.g. complement all bits and
add 1)
• Review Digital Logic I and II courses
Arithmetic with Signed Numbers
- All arithmetic (addition/subtraction) performed
on full binary number, including sign.
- Hardware treats signed number as unsigned
from perspective of requested operation
- Benefit is that we do not need to do anything
special to manage sign of operands or result
- Disadvantage, seems counterintuitive.
Week 2: Addressing Modes (^65)
2s Complement Ranges
Range of 2’s complement numbers:
8-bit Reg. -128 to +127 decimal
16-bit reg. -32,768 to 32,767 decimal
Complement and add 1
C Flag (for 2s Complement
Numbers)
• C flag set to ‘1’ if
- Carry out from MSB for addition
- Borrow from MSB for subtraction
• C flag set to ‘0’ if neither of the above apply
• Several hardware implementations possible
to determine value of C
Week 2: Addressing Modes (^67)
Methods to Determine C Flag Value
- Method 1: more like how we do it hand –Explicitly monitor for carry or borrow,
- Method 2: possible implementation –Express result expressed as 9/17 bit quantity –For addition, extra bit is the carry flag –For subtraction—carry determined from extra bit - borrow from fictitious 9th^ bit in first subtrahend that is always “1” - carry is the complement of the extra 9th/17th^ bit from result
- Method 3: possible implementation—minimum
hardware?
–Examine operands and result, develop Boolean equations for C –Method 3 is how the carry is documented in the 68HC manual
Signed Addition Example
MSB LSB 56
-53^11001011
C
Add 56 and –53 ($CB), and determine if carry bit is set or not. LDAA # LDAB #- ABA
The result is 8 bits, we don't use C flag as the 9th bit since the numbers are taken as signed
Week 2: Addressing Modes (^73)
Add -120 and -10, and determine if overflow bit is set or not.
MSB LSB
-
-10^11110110
-130^10111111
LDAA #- ADDA #-
The result exceeds the range of 8 bit 2s complement numbers (i.e. less than -128) OVERFLOW!!!
2s Complement Overflow Example 2
Add 80 and 45, and determine if overflow bit is set or not.
MSB LSB 80
45 1 1 1 1 0 1 1 0
(^1250011011 )
LDAA # ADDA #
The result does NOT exceeds the range of 8 bit 2s complement number NO OVERFLOW!!!
2s Complement Overflow Example 3
Week 2: Addressing Modes (^75)
In More Simple Terms
Outside
Inside
Range Limit V Flag
Negative Flag
• N-bit indicates state of msb of a result
• If msb = 1 => N-flag = 1
• If msb = 0 => N-flag = 0
• N-bit is used in 2’s complement arithmetic
to indicate the sign of a number
• So if V-flag = 0 => correct answer
=> N-flag valid sign
Week 2: Addressing Modes (^77)
N Flag
- 6811 treats all numbers as 2’s complement binary numbers
- Subtraction is performed using 2’s complement arithmetic
- N Flag is simply the MSB of the result
-^11
+^00
Value Value of MSB Value of N-flag
Half Carry (H flag)
- Used only for BCD (Binary Coded Decimal)
operations. (They will be discussed later)
- H-flag updated only by ABA, ADDA, ADDB,
ADCA, ADCB
- To do decimal arithmetic, the 68HC11 does
arithmetic in binary and then uses H and C to
adjust the calculation to give a proper decimal
result.
Week 2: Addressing Modes (^79)
Zero Flag (Z flag)
Z bit is set to a logic ‘1’ when the
result is ‘0’, otherwise Z=0.
Zero Flag Example 1
Add 50 and -50, and determine zero flag is set or not.
MSB LSB 50
-50^11001110
(^010000000 )
LDAA # ADDA #-
The 8bit result is all zeros. Therefore, Z flag is set. Note also that C=1 and V=0.
